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-rw-r--r--target/mips/cpu.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c45744c5c..b9e227a30e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MSA implementation */
+static inline bool ase_msa_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MSAP);
+}
+
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{