diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 33ef7926e6..47eb3119cb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.4) + * destination vector register is v0 and LMUL > 1. (Section 11.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { |