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* target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens2019-05-241-1/+3
| | | | | | | | | There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: More accurate handling of `sip` CSRJonathan Behrens2019-05-241-2/+5
| | | | | | | | | | | According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip register are read-only." Further, if an interrupt is not delegated to mode x, then "the corresponding bits in xip [...] should appear to be hardwired to zero. This patch implements both of those requirements. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add checks for several RVC reserved operandsRichard Henderson2019-05-242-3/+14
| | | | | | | | | C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
| | | | | | | | Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis2019-05-241-9/+8Star
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Revieweb-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Improve the scause logicAlistair Francis2019-05-241-1/+1
| | | | | | | | No functional change, just making the code easier to read. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-242-8/+27
| | | | | | | | | | | The requirement of holding the iothread_mutex is burdersome when swapping the background and foreground registers in the Hypervisor extension. To avoid the requrirement let's set the interrupt asynchronously. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: spike: Add a generic spike machineAlistair Francis2019-05-242-1/+111
| | | | | | | | | | | | Add a generic spike machine (not tied to a version) and deprecate the spike mahines that are tied to a specific version. As we can now specify the CPU via the command line we no londer need specific versions of the spike machines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Deprecate the generic no MMU CPUsAlistair Francis2019-05-241-0/+6
| | | | | | | | | These can now be specified via the command line so we no longer need these. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-244-2/+27
| | | | | | | | | | | | At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Create settable CPU propertiesAlistair Francis2019-05-242-0/+57
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: virt: Allow specifying a CPU via commandlineAlistair Francis2019-05-241-1/+2
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* linux-user/riscv: Add the CPU type as a commentAlistair Francis2019-05-241-0/+1
| | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens2019-05-241-1/+0Star
| | | | | | | Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Remove spaces from register namesRichard Henderson2019-05-241-8/+8
| | | | | | | | These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-242-9/+24
| | | | | | | | | | The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-246-151/+67Star
| | | | | | | | | This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-243-69/+29Star
| | | | | | | | | This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-243-53/+12Star
| | | | | | | | | Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2019-05-242-170/+58Star
| | | | | | | | | In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-242-7/+4Star
| | | | | | | | | The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-242-3/+25
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-243-12/+32
| | | | | | | | | | | | | | | This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single stepping handling in places where it was previously ignored such as jalr and system branch instructions (ecall, mret, sret, etc.). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Do not allow sfence.vma from user modeJonathan Behrens2019-05-241-3/+4
| | | | | | | | | | The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* SiFive RISC-V GPIO DeviceFabien Chouteau2019-05-247-4/+501
| | | | | | | | | | | | QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* Merge remote-tracking branch ↵Peter Maydell2019-05-246-62/+143
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging Add /proc/hardware and /proc/cpuinfo, update SIOCXXX ioctls, fix shmat emulation, add nanoseconds in stat, init field fp_abi on mips # gpg: Signature made Fri 24 May 2019 12:24:36 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-4.1-pull-request: linux-user: Pass through nanosecond timestamp components for stat syscalls linux-user: Align mmap_find_vma to host page size linux-user: Fix shmat emulation by honoring host SHMLBA linux-user: Sanitize interp_info and, for mips only, init field fp_abi linux-user: Add support for SIOC<G|S>IFPFLAGS ioctls for all targets linux-user: Add support for SIOCSPGRP ioctl for all targets linux-user: Fix support for SIOCATMARK and SIOCGPGRP ioctls for xtensa linux-user: add pseudo /proc/hardware for m68k linux-user: add pseudo /proc/cpuinfo for sparc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * linux-user: Pass through nanosecond timestamp components for stat syscallsChen-Yu Tsai2019-05-242-18/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Linux 2.6 the stat syscalls have mostly supported nanosecond components for each of the file-related timestamps. QEMU user mode emulation currently does not pass through the nanosecond portion of the timestamp, even when the host system fills in the value. This results in a mismatch when run on subsecond resolution filesystems such as ext4 or XFS. An example of this leading to inconsistency is cross-debootstraping a full desktop root filesystem of Debian Buster. Recent versions of fontconfig store the full timestamp (instead of just the second portion) of the directory in its per-directory cache file, and checks this against the directory to see if the cache is up-to-date. With QEMU user mode emulation, the timestamp stored is incorrect, and upon booting the rootfs natively, fontconfig discovers the mismatch, and proceeds to rebuild the cache on the comparatively slow machine (low-power ARM vs x86). This stalls the first attempt to open whatever application that incorporates fontconfig. This patch renames the "unused" padding trailing each timestamp element to its nanosecond counterpart name if such an element exists in the kernel sources for the given platform. Not all do. Then have the syscall wrapper fill in the nanosecond portion if the host supports it, as specified by the _POSIX_C_SOURCE and _XOPEN_SOURCE feature macros. Recent versions of glibc only use stat64 and newfstatat syscalls on 32-bit and 64-bit platforms respectively. The changes in this patch were tested by directly calling the stat, stat64 and newfstatat syscalls directly, in addition to the glibc wrapper, on arm and aarch64 little endian targets. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Message-Id: <20190522162147.26303-1-wens@kernel.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Align mmap_find_vma to host page sizeRichard Henderson2019-05-241-0/+2
| | | | | | | | | | | | | | | | | | | | This can avoid stack allocation failures for i386 guest on ppc64 (64k page) host. Suggested-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190519201953.20161-14-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Fix shmat emulation by honoring host SHMLBARichard Henderson2019-05-244-42/+50
| | | | | | | | | | | | | | | | | | | | | | For those hosts with SHMLBA > getpagesize, we don't automatically select a guest address that is compatible with the host. We can achieve this by boosting the alignment of guest_base and by adding an extra alignment argument to mmap_find_vma. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190519201953.20161-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Sanitize interp_info and, for mips only, init field fp_abiDaniel Santos2019-05-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sanitize interp_info structure in load_elf_binary() and, for MIPS only, init its field fp_abi to MIPS_ABI_FP_UNKNOWN. This fixes appearances of "Unexpected FPU mode" message in some MIPS use cases. Currently, this bug is a complete stopper for some MIPS binaries. In load_elf_binary(), struct image_info interp_info is used without being properly initialized. One result is that when the ELF's program header doesn't contain an entry for the ABI flags, then the value of the struct image_info's fp_abi field is set to whatever happened to be in stack memory at the time. Backporting to 4.0 and, if possible, to 3.1 is recommended. Fixes: https://bugs.launchpad.net/qemu/+bug/1825002 Signed-off-by: Daniel Santos <daniel.santos@pobox.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1558282527-22183-6-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Add support for SIOC<G|S>IFPFLAGS ioctls for all targetsNeng Chen2019-05-222-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for getting and setting extended private flags of a network device via SIOCSIFPFLAGS and SIOCGIFPFLAGS ioctls. The ioctl numeric values are platform-independent and determined by the file include/uapi/linux/sockios.h in Linux kernel source code: #define SIOCSIFPFLAGS 0x8934 #define SIOCGIFPFLAGS 0x8935 These ioctls get (or set) the field ifr_flags of type short in the structure ifreq. Such functionality is achieved in QEMU by using MK_STRUCT() and MK_PTR() macros with an appropriate argument, as it was done for existing similar cases. Signed-off-by: Neng Chen <nchen@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1554839486-3527-1-git-send-email-aleksandar.markovic@rt-rk.com> Message-Id: <1558282527-22183-4-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Add support for SIOCSPGRP ioctl for all targetsAleksandar Markovic2019-05-222-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for setting the process (or process group) to receive SIGIO or SIGURG signals when I/O becomes possible or urgent data is available, using SIOCSPGRP ioctl. The ioctl numeric values for SIOCSPGRP are platform-dependent and are determined by following files in Linux kernel source tree: arch/ia64/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902 arch/mips/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t) arch/parisc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902 arch/sh/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t) arch/xtensa/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t) arch/alpha/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t) arch/sparc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902 include/uapi/asm-generic/sockios.h:#define SIOCSPGRP 0x8902 Hence the different definition for alpha, mips, sh4, and xtensa. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1558282527-22183-3-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Fix support for SIOCATMARK and SIOCGPGRP ioctls for xtensaAleksandar Markovic2019-05-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa by correcting corresponding macro definition. Values for TARGET_SIOCATMARK and TARGET_SIOCGPGRP are determined by Linux kernel. Following relevant lines (obtained by grep) are from the kernel source tree: arch/ia64/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905 arch/mips/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int) arch/parisc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905 arch/sh/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int) arch/xtensa/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int) arch/alpha/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int) arch/sparc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905 include/uapi/asm-generic/sockios.h:#define SIOCATMARK 0x8905 arch/ia64/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904 arch/mips/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t) arch/parisc/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904 arch/sh/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t) arch/xtensa/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t) arch/alpha/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t) arch/sparc/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904 include/uapi/asm-generic/sockios.h:#define SIOCGPGRP 0x8904 It is visible from above that xtensa should have the same definitions as alpha, mips and sh4 already do. This patch brings QEMU to the accurate state wrt these two ioctls. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1558282527-22183-2-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: add pseudo /proc/hardware for m68kLaurent Vivier2019-05-221-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debian console-setup uses /proc/hardware to guess the keyboard layout. If the file /proc/hardware cannot be opened, the installation fails. This patch adds a pseudo /proc/hardware file to report the model of the machine. Instead of reporting a known and fake model, it reports "qemu-m68k", which is true, and avoids to set the configuration for an Amiga/Apple/Atari and let the user to chose the good one. Bug: https://github.com/vivier/qemu-m68k/issues/34 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190517133149.19593-3-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: add pseudo /proc/cpuinfo for sparcLaurent Vivier2019-05-221-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPARC libc6 debian package wants to check the cpu level to be installed or not: WARNING: This machine has a SPARC V8 or earlier class processor. Debian lenny and later does not support such old hardware any longer. To avoid this, it only needs to know if the machine type is sun4u or sun4v, for that it reads the information from /proc/cpuinfo. Fixes: 9a93c152fcdb4ab2cd85094487b33578fd693915 ("linux-user: fix UNAME_MACHINE for sparc/sparc64") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190517133149.19593-2-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190524-pull-request' ↵Peter Maydell2019-05-245-21/+88
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ramfb: misc improvements. # gpg: Signature made Fri 24 May 2019 09:56:59 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190524-pull-request: hw/display/ramfb: initialize fw-config space with xres/ yres hw/display/ramfb: lock guest resolution after it's set hw/display/ramfb: fix guest memory un-mapping Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/display/ramfb: initialize fw-config space with xres/ yresHou Qiming2019-05-245-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If xres / yres were specified in QEMU command line, write them as an initial resolution to the fw-config space on guest reset, which a later BIOS / OVMF patch can take advantage of. Signed-off-by: HOU Qiming <hqm03ster@gmail.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-id: 20190513115731.17588-4-marcel.apfelbaum@gmail.com [fixed malformed patch] Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | hw/display/ramfb: lock guest resolution after it's setHou Qiming2019-05-241-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only allow one resolution change per guest boot, which prevents a crash when the guest writes garbage to the configuration space (e.g. when rebooting). Signed-off-by: HOU Qiming <hqm03ster@gmail.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-id: 20190513115731.17588-3-marcel.apfelbaum@gmail.com [fixed malformed patch] Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | hw/display/ramfb: fix guest memory un-mappingHou Qiming2019-05-241-13/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pulled back the `qemu_create_displaysurface_guestmem` function to create the display surface so that the guest memory gets properly unmapped. Signed-off-by: HOU Qiming <hqm03ster@gmail.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-id: 20190513115731.17588-2-marcel.apfelbaum@gmail.com [rename the new functions and use QEMU coding style] Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190522' into stagingPeter Maydell2019-05-2414-187/+619
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc gvec improvements # gpg: Signature made Wed 22 May 2019 23:25:48 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190522: tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store tcg/aarch64: Allow immediates for vector ORR and BIC tcg/aarch64: Build vector immediates with two insns tcg/aarch64: Use MVNI in tcg_out_dupi_vec tcg/aarch64: Split up is_fimm tcg/aarch64: Support vector bitwise select value tcg/i386: Use umin/umax in expanding unsigned compare tcg/i386: Remove expansion for missing minmax tcg/i386: Support vector comparison select value tcg: Add TCG_OPF_NOT_PRESENT if TCG_TARGET_HAS_foo is negative tcg: Expand vector minmax using cmp+cmpsel tcg: Introduce do_op3_nofail for vector expansion tcg: Add support for vector compare select tcg: Add support for vector bitwise select tcg: Fix missing checks and clears in tcg_gen_gvec_dup_mem tcg/i386: Fix dupi/dupm for avx1 and 32-bit hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/storeRichard Henderson2019-05-221-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This instruction raises #GP, aka SIGSEGV, if the effective address is not aligned to 16-bytes. We have assertions in tcg-op-gvec.c that the offset from ENV is aligned, for vector types <= V128. But the offset itself does not validate that the final pointer is aligned -- one must also remember to use the QEMU_ALIGNED() attribute on the vector member within ENV. PowerPC Altivec has vector load/store instructions that silently discard the low 4 bits of the address, making alignment mistakes difficult to discover. Aid that by making the most popular host visibly signal the error. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | tcg/aarch64: Allow immediates for vector ORR and BICRichard Henderson2019-05-221-7/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The allows immediates to be used for ORR and BIC, as well as the trivial inversions, ORC and AND. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | tcg/aarch64: Build vector immediates with two insnsRichard Henderson2019-05-221-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use MOVI+ORR or MVNI+BIC in order to build some vector constants, as opposed to dropping them to the constant pool. This includes all 16-bit constants and a similar set of 32-bit constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | tcg/aarch64: Use MVNI in tcg_out_dupi_vecRichard Henderson2019-05-221-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The compliment of a subset of immediates can be computed with a single instruction. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | tcg/aarch64: Split up is_fimmRichard Henderson2019-05-221-84/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several sub-classes of vector immediate, and only MOVI can use them all. This will enable usage of MVNI and ORRI, which use progressively fewer sub-classes. This patch adds no new functionality, merely splits the function and moves part of the logic into tcg_out_dupi_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | tcg/aarch64: Support vector bitwise select valueRichard Henderson2019-05-222-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The instruction set has 3 insns that perform the same operation, only varying in which operand must overlap the destination. We can represent the operation without overlap and choose based on the operands seen. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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