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* tests/acceptance: test hot(un)plug of ccw devicesCornelia Huck2020-12-211-0/+24
| | | | | | | | | | | Hotplug a virtio-net-ccw device, and then hotunplug it again. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20201208122843.147186-1-cohuck@redhat.com>
* target/s390x: Improve SUB LOGICAL WITH BORROWRichard Henderson2020-12-215-73/+45Star
| | | | | | | | | | | Now that SUB LOGICAL outputs borrow, we can use that as input directly. It also means we can re-use CC_OP_SUBU and produce an output borrow directly from SUB LOGICAL WITH BORROW. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-5-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Improve cc computation for SUBTRACT LOGICALRichard Henderson2020-12-215-82/+43Star
| | | | | | | | | | | | | | | | The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-4-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Improve ADD LOGICAL WITH CARRYRichard Henderson2020-12-215-67/+34Star
| | | | | | | | | | | Now that ADD LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ADDU and produce an output carry directly from ADD LOGICAL WITH CARRY. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Improve cc computation for ADD LOGICALRichard Henderson2020-12-215-74/+97
| | | | | | | | | | | | | | The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* qga/commands-posix: Send CCW address on s390x with the fsinfo dataThomas Huth2020-12-212-1/+53
| | | | | | | | | | | We need the CCW address on the libvirt side to correctly identify the disk, so add this information to the GuestDiskAddress on s390x. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Michael Roth <michael.roth@amd.com> Message-Id: <20201127082353.448251-1-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* MAINTAINERS: move my git tree to gitlabCornelia Huck2020-12-211-5/+5
| | | | | | | | | I push to gitlab anyway to get some CI coverage, so let's make it my primary tree to avoid workflow duplication. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201214132628.56019-1-cohuck@redhat.com>
* s390x: pv: Fence additional unavailable SCLP facilities for PV guestsJanosch Frank2020-12-212-3/+61
| | | | | | | | | | | | There's no VSIE support for a protected guest, so let's better not advertise it and its support facilities. Fixes: c3347ed0d2ee ("s390x: protvirt: Support unpack facility") Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20201211105109.2913-1-frankja@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2020-12-1820-307/+434
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging A collection of RISC-V improvements: - Improve the sifive_u DTB generation - Add QSPI NOR flash to Microchip PFSoC - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions - Fix some mstatus mask defines - Ibex PLIC improvements - OpenTitan memory layout update - Initial steps towards support for 32-bit CPUs on 64-bit builds # gpg: Signature made Fri 18 Dec 2020 05:59:42 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20201217-1: (23 commits) riscv/opentitan: Update the OpenTitan memory layout hw/riscv: Use the CPU to determine if 32-bit target/riscv: cpu: Set XLEN independently from target target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: cpu: Remove compile time XLEN checks target/riscv: Specify the XLEN for CPUs target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: fpu_helper: Match function defs in HELPER macros hw/riscv: sifive_u: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: boot: Remove compile time XLEN checks riscv: virt: Remove target macro conditionals riscv: spike: Remove target macro conditionals target/riscv: Add a TYPE_RISCV_CPU_BASE CPU hw/riscv: Expand the is 32-bit check to support more CPUs intc/ibex_plic: Clear interrupts that occur during claim process target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR target/riscv: Fix the bug of HLVX/HLV/HSV ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-182-30/+74
| | | | | | | | | | | | | | | | OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
| * hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-185-37/+29Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using string compares to determine if a RISC-V machine is using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids us having to maintain a list of CPU names to compare against. This commit also fixes the name of the function to match the riscv_cpu_is_32bit() function. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
| * target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
| * target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-182-88/+92
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
| * target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis2020-12-181-5/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
| * target/riscv: cpu: Remove compile time XLEN checksAlistair Francis2020-12-181-9/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
| * target/riscv: Specify the XLEN for CPUsAlistair Francis2020-12-181-10/+23
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
| * target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-182-0/+11
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
| * target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2020-12-182-24/+8Star
| | | | | | | | | | | | | | | | | | | | Update the function definitions generated in helper.h to match the actual function implementations. Also remove all compile time XLEN checks when building. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 614c369cb0000d070873a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
| * hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-181-25/+30
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
| * hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-181-21/+24
| | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
| * hw/riscv: virt: Remove compile time XLEN checksAlistair Francis2020-12-181-15/+17
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
| * hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-185-31/+39
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
| * riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-182-7/+1Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
| * riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-182-7/+1Star
| | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
| * target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis2020-12-181-0/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
| * hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis2020-12-181-1/+11
| | | | | | | | | | | | | | | | | | | | | | Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
| * intc/ibex_plic: Clear interrupts that occur during claim processAlistair Francis2020-12-181-3/+10
| | | | | | | | | | | | | | | | | | | | | | Previously if an interrupt occured during the claim process (after the interrupt is claimed but before it's completed) it would never be cleared. This patch ensures that we also clear the hidden_pending bits as well. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Jackie Ke <jackieke724@hotmail.com> Message-id: 4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
| * target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson2020-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang2020-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We found that the hypervisor virtual-machine load and store instructions, included HLVX/HLV/HSV, couldn't access guest userspace memory. In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow: "As usual when V=1, two-stage address translation is applied, and the HS-level sstatus.SUM is ignored." But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV accesses guest userspace memory. So this patch fixes it. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201130012810.899-1-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/core/register.c: Don't use '#' flag of printf formatXinhao Zhang2020-12-181-8/+8
| | | | | | | | | | | | | | | | | | | | | | Fix code style. Don't use '#' flag of printf format ('%#') in format strings, use '0x' prefix instead Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> Signed-off-by: Kai Deng <dengkai1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-182-0/+24
| | | | | | | | | | | | | | | | | | | | Add QSPI NOR flash definition for Microchip PolarFire SoC. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-181-0/+15
|/ | | | | | | | | | | The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201111094725.3768755-1-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge remote-tracking branch ↵Peter Maydell2020-12-1763-766/+956
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging x86 queue, 2020-12-17 Features: * AVX512_FP16 feature (Cathy Zhang) Cleanups: * accel code cleanup (Claudio Fontana) * hyperv initialization cleanup (Vitaly Kuznetsov) # gpg: Signature made Thu 17 Dec 2020 18:44:45 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost-gl/tags/x86-next-pull-request: cpu: Remove unnecessary noop methods tcg: Make CPUClass.debug_excp_handler optional tcg: make CPUClass.cpu_exec_* optional tcg: cpu_exec_{enter,exit} helpers i386: tcg: remove inline from cpu_load_eflags i386: move TCG cpu class initialization to tcg/ x86/cpu: Add AVX512_FP16 cpu feature i386: move hyperv_limits initialization to x86_cpu_realizefn() i386: move hyperv_version_id initialization to x86_cpu_realizefn() i386: move hyperv_interface_id initialization to x86_cpu_realizefn() i386: move hyperv_vendor_id initialization to x86_cpu_realizefn() i386: move cpu dump out of helper.c into cpu-dump.c i386: move TCG accel files into tcg/ i386: hvf: remove stale MAINTAINERS entry for old hvf stubs i386: move hax accel files into hax/ i386: move whpx accel files into whpx/ i386: move kvm accel files into kvm/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * cpu: Remove unnecessary noop methodsEduardo Habkost2020-12-161-13/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | In the previous commits we made cpu_exec_* and debug_excp_handler optional, so we can now remove these no-op handlers. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201212155530.23098-13-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * tcg: Make CPUClass.debug_excp_handler optionalEduardo Habkost2020-12-161-1/+3
| | | | | | | | | | | | | | | | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-12-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * tcg: make CPUClass.cpu_exec_* optionalEduardo Habkost2020-12-161-3/+8
| | | | | | | | | | | | | | | | | | | | | | This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-11-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * tcg: cpu_exec_{enter,exit} helpersEduardo Habkost2020-12-161-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-10-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: tcg: remove inline from cpu_load_eflagsClaudio Fontana2020-12-162-13/+15
| | | | | | | | | | | | | | | | | | | | make it a regular function. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-9-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move TCG cpu class initialization to tcg/Claudio Fontana2020-12-1619-148/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to do this, we need to take code out of cpu.c and helper.c, and also move some prototypes from cpu.h, for code that is needed in tcg/xxx_helper.c, and which in turn is part of the callbacks registered by the class initialization. Therefore, do some shuffling of the parts of cpu.h that are only relevant for tcg/, and put them in tcg/helper-tcg.h For FT0 and similar macros, put them in tcg/fpu-helper.c since they are used only there. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-8-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * x86/cpu: Add AVX512_FP16 cpu featureCathy Zhang2020-12-162-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AVX512 Half-precision floating point (FP16) has better performance compared to FP32 if the presicion or magnitude requirements are met. It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23]. Refer to https://software.intel.com/content/www/us/en/develop/download/\ intel-architecture-instruction-set-extensions-programming-reference.html Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move hyperv_limits initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-1/+18
| | | | | | | | | | | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_limits initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-5-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move hyperv_version_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-2/+17
| | | | | | | | | | | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_version_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-4-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move hyperv_interface_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-6/+19
| | | | | | | | | | | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_interface_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-3-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-17/+34
| | | | | | | | | | | | | | | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() itself. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-2-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move cpu dump out of helper.c into cpu-dump.cClaudio Fontana2020-12-164-514/+539
| | | | | | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-7-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move TCG accel files into tcg/Claudio Fontana2020-12-1616-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved cc_helper_template.h to tcg/ too] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20201212155530.23098-6-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: hvf: remove stale MAINTAINERS entry for old hvf stubsClaudio Fontana2020-12-161-1/+0Star
| | | | | | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-5-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move hax accel files into hax/Claudio Fontana2020-12-1613-11/+12
| | | | | | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-4-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move whpx accel files into whpx/Claudio Fontana2020-12-168-10/+7Star
| | | | | | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-3-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: move kvm accel files into kvm/Claudio Fontana2020-12-1625-22/+26
|/ | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-2-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 09:27:02 +0100