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* tcg-s390: Remove W constraintRichard Henderson2014-04-191-24/+19Star
* tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson2014-04-191-1/+7
* tcg-ppc64: Use the type parameter to tcg_target_const_matchRichard Henderson2014-04-191-1/+9
* tcg-aarch64: Remove w constraintRichard Henderson2014-04-191-22/+18Star
* tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson2014-04-1911-13/+13
* tcg: Fix out of range shift in deposit optimizationsRichard Henderson2014-04-191-6/+4Star
* tci: Mask shift counts to avoid undefined behaviorRichard Henderson2014-04-191-10/+10
* tcg: Mask shift quantities while foldingRichard Henderson2014-04-191-15/+20
* tcg: Use "unspecified behavior" for shiftsRichard Henderson2014-04-191-5/+13
* tcg: Fix warning (1 bit signed bitfield entry) and replace int by boolStefan Weil2014-04-195-13/+13
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140417-...Peter Maydell2014-04-1727-805/+2415
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| * target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée2014-04-171-1/+1
| * arm: translate.c: Fix smlald InstructionPeter Crosthwaite2014-04-171-11/+23
| * net: cadence_gem: Make phy respond to broadcastPeter Crosthwaite2014-04-171-2/+2
| * misc: zynq_slcr: Make DB_PRINTs always compilePeter Crosthwaite2014-04-171-6/+8
| * misc: zynq_slcr: Convert SBD::init to object initPeter Crosthwaite2014-04-171-8/+5Star
| * misc: zynq-slcr: RewritePeter Crosthwaite2014-04-171-378/+294Star
| * allwinner-emac: update irq status after writes to interrupt registersBeniamino Galvani2014-04-171-0/+2
| * allwinner-emac: set autonegotiation complete bit on link upBeniamino Galvani2014-04-172-2/+3
| * allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani2014-04-173-1/+41
| * allwinner-a10-pit: use level triggered interruptsBeniamino Galvani2014-04-171-1/+14
| * allwinner-a10-pit: avoid generation of spurious interruptsBeniamino Galvani2014-04-172-13/+24
| * allwinner-a10-pic: fix behaviour of pending registerBeniamino Galvani2014-04-171-1/+7
| * allwinner-a10-pic: set vector address when an interrupt is pendingBeniamino Galvani2014-04-171-4/+10
| * timer: cadence_ttc: Fix match register write logicPeter Crosthwaite2014-04-171-0/+2
| * target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang2014-04-171-2/+0Star
| * target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell2014-04-174-3/+13
| * target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell2014-04-171-4/+8
| * target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell2014-04-171-1/+1
| * target-arm: Implement CBAR for Cortex-A57Peter Maydell2014-04-175-9/+42
| * target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell2014-04-171-0/+55
| * target-arm: Implement RVBAR registerPeter Maydell2014-04-173-0/+16
| * target-arm: Implement AArch64 address translation operationsPeter Maydell2014-04-172-31/+25Star
| * target-arm: Implement auxiliary fault status registersPeter Maydell2014-04-171-0/+9
| * target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell2014-04-171-5/+91
| * target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell2014-04-171-18/+43
| * target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell2014-04-171-1/+0Star
| * target-arm: Implement ISR_EL1 registerPeter Maydell2014-04-171-0/+18
| * target-arm: Implement AArch64 view of ACTLRPeter Maydell2014-04-171-1/+2
| * target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell2014-04-172-16/+19
| * target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell2014-04-171-29/+44
| * target-arm: Add Cortex-A57 processorPeter Maydell2014-04-171-0/+43
| * target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-175-2/+23
| * target-arm: Implement AArch64 EL1 exception handlingRob Herring2014-04-176-0/+143
| * target-arm: Move arm_log_exception() into internals.hPeter Maydell2014-04-172-31/+31
| * target-arm: Implement AArch64 SPSR_EL1Peter Maydell2014-04-175-11/+40
| * target-arm: Implement SP_EL0, SP_EL1Peter Maydell2014-04-176-7/+100
| * target-arm: Add AArch64 ELR_EL1 register.Peter Maydell2014-04-174-4/+24
| * target-arm: Implement AArch64 views of fault status and data registersRob Herring2014-04-173-18/+29
| * target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell2014-04-172-10/+16
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