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* hw/ppc: Delete unused ppc405cr_init() codePeter Maydell2021-01-192-351/+0Star
* hw/ppc/sam460ex: Drop use of ppcuic_init()Peter Maydell2021-01-191-16/+53
* Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell2021-01-184-5/+26
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| * hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé2021-01-181-3/+5
| * misc/mos6522: Use timer_free() in the finalize function to avoid memleakGan Qixin2021-01-181-0/+9
| * pl031: Use timer_free() in the finalize function to avoid memleaksGan Qixin2021-01-181-0/+8
| * hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé2021-01-181-2/+4
* | Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell2021-01-1864-336/+982
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| * | semihosting: Implement SYS_ISERRORKeith Packard2021-01-181-0/+4
| * | semihosting: Implement SYS_TMPNAMKeith Packard2021-01-181-2/+19
| * | semihosting: Implement SYS_ELAPSED and SYS_TICKFREQKeith Packard2021-01-183-0/+22
| * | riscv: Add semihosting support for user modeKito Cheng2021-01-181-0/+5
| * | riscv: Add semihosting supportKeith Packard2021-01-1813-12/+162
| * | semihosting: Support SYS_HEAPINFO when env->boot_info is not setKeith Packard2021-01-181-1/+42
| * | semihosting: Change internal common-semi interfaces to use CPUState *Keith Packard2021-01-181-163/+186
| * | semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-187-19/+59
| * | semihosting: Move ARM semihosting code to shared directoriesKeith Packard2021-01-1812-5/+13
| * | target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-183-47/+41Star
| * | gdbstub: ensure we clean-up when terminatedAlex Bennée2021-01-181-0/+2
| * | gdbstub: drop gdbserver_cleanup in favour of gdb_exitAlex Bennée2021-01-183-11/+12
| * | gdbstub: drop CPUEnv from gdb_exit()Alex Bennée2021-01-187-9/+9
| * | gdbstub: add support to Xfer:auxv:read: packetLirong Yuan2021-01-184-0/+121
| * | gdbstub: implement a softmmu based testAlex Bennée2021-01-189-12/+181
| * | Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test"Alex Bennée2021-01-181-3/+1Star
| * | configure: gate our use of GDB to 8.3.1 or aboveAlex Bennée2021-01-181-2/+5
| * | test/guest-debug: echo QEMU command as wellAlex Bennée2021-01-181-0/+1
| * | scripts/checkpatch.pl: fix git-show invocation to include diffstatAlex Bennée2021-01-181-1/+1
| * | gitlab: migrate the minimal tools and unit tests from TravisAlex Bennée2021-01-182-10/+3Star
| * | Fix build with new yank feature by adding stubsLukas Straub2021-01-183-0/+31
| * | gitlab: move docs and tools build across from TravisAlex Bennée2021-01-182-22/+22
| * | docker: expand debian-amd64 image to include tag toolsAlex Bennée2021-01-181-1/+4
| * | Makefile: wrap cscope in quiet-command callsAlex Bennée2021-01-181-3/+11
| * | Makefile: wrap etags in quiet-command callsAlex Bennée2021-01-181-2/+7
| * | Makefile: wrap ctags in quiet-command callsAlex Bennée2021-01-181-2/+7
| * | Add newline when generating DockerfileAlessandro Di Federico2021-01-181-2/+2
| * | shippable.yml: Remove jobs duplicated on Gitlab-CIPhilippe Mathieu-Daudé2021-01-181-13/+1Star
| * | Makefile: add GNU global tags supportAlex Bennée2021-01-182-1/+16
| * | tests/docker: Remove Debian 9 remnant linesPhilippe Mathieu-Daudé2021-01-181-1/+0Star
* | | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell2021-01-1820-902/+463Star
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| * | riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-165-22/+20Star
| * | target/riscv: Remove built-in GDB XML files for CSRsBin Meng2021-01-166-504/+4Star
| * | target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-163-264/+58Star
| * | target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-162-84/+249
| * | target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-162-9/+9
| * | hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwriteGreen Wan2021-01-161-8/+23
| * | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1Star
| * | target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-163-2/+8
| * | RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra2021-01-161-4/+4
| * | gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
| * | hw/block: m25p80: Implement AAI-WP command support for SST flashesXuzhou Cheng2021-01-161-0/+73
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