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* pc-bios: s390x: Rename PSW_MASK_ZMODE to PSW_MASK_64Janosch Frank2020-07-021-1/+1
| | | | | | | | | | This constant enables 64 bit addressing, not the ESAME architecture, so it shouldn't be named ZMODE. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200624075226.92728-7-frankja@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* pc-bios: s390x: Get rid of magic offsets into the lowcoreJanosch Frank2020-07-022-11/+14
| | | | | | | | | | | | If we have a lowcore struct that has members for offsets that we want to touch, why not use it? Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200624075226.92728-5-frankja@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* pc-bios: s390x: Move sleep and yield to helper.hJanosch Frank2020-07-024-18/+19
| | | | | | | | | | | They are definitely helper functions. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20200624075226.92728-4-frankja@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* pc-bios: s390x: Consolidate timing functions into time.hJanosch Frank2020-07-027-31/+36
| | | | | | | | | | Let's consolidate timing related functions into one header. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20200624075226.92728-3-frankja@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* pc-bios: s390x: cio.c cleanup and compile fixJanosch Frank2020-07-021-18/+22
| | | | | | | | | | | | | | | | Let's initialize the structs at the beginning to ease reading and also zeroing all other fields. This also makes the compiler stop complaining about sense_id_ccw.flags being ored into when it's not initialized. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200624075226.92728-2-frankja@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/misc/pca9552: Add missing TypeInfo::class_size fieldPhilippe Mathieu-Daudé2020-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding the generic PCA955xClass in commit 736132e455, we forgot to set the class_size field. Fill it now to avoid: (gdb) run -machine mcimx6ul-evk -m 128M -display none -serial stdio -kernel ./OS.elf Starting program: ../../qemu/qemu/arm-softmmu/qemu-system-arm -machine mcimx6ul-evk -m 128M -display none -serial stdio -kernel ./OS.elf double free or corruption (!prev) Thread 1 "qemu-system-arm" received signal SIGABRT, Aborted. __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50 (gdb) where #0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50 #1 0x00007ffff75d8859 in __GI_abort () at abort.c:79 #2 0x00007ffff76433ee in __libc_message (action=action@entry=do_abort, fmt=fmt@entry=0x7ffff776d285 "%s\n") at ../sysdeps/posix/libc_fatal.c:155 #3 0x00007ffff764b47c in malloc_printerr (str=str@entry=0x7ffff776f690 "double free or corruption (!prev)") at malloc.c:5347 #4 0x00007ffff764d12c in _int_free (av=0x7ffff779eb80 <main_arena>, p=0x5555567a3990, have_lock=<optimized out>) at malloc.c:4317 #5 0x0000555555c906c3 in type_initialize_interface (ti=ti@entry=0x5555565b8f40, interface_type=0x555556597ad0, parent_type=0x55555662ca10) at qom/object.c:259 #6 0x0000555555c902da in type_initialize (ti=ti@entry=0x5555565b8f40) at qom/object.c:323 #7 0x0000555555c90d20 in type_initialize (ti=0x5555565b8f40) at qom/object.c:1028 $ valgrind --track-origins=yes qemu-system-arm -M mcimx6ul-evk -m 128M -display none -serial stdio -kernel ./OS.elf ==77479== Memcheck, a memory error detector ==77479== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al. ==77479== Using Valgrind-3.15.0 and LibVEX; rerun with -h for copyright info ==77479== Command: qemu-system-arm -M mcimx6ul-evk -m 128M -display none -serial stdio -kernel ./OS.elf ==77479== ==77479== Invalid write of size 2 ==77479== at 0x6D8322: pca9552_class_init (pca9552.c:424) ==77479== by 0x844D1F: type_initialize (object.c:1029) ==77479== by 0x844D1F: object_class_foreach_tramp (object.c:1016) ==77479== by 0x4AE1057: g_hash_table_foreach (in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0.6400.2) ==77479== by 0x8453A4: object_class_foreach (object.c:1038) ==77479== by 0x8453A4: object_class_get_list (object.c:1095) ==77479== by 0x556194: select_machine (vl.c:2416) ==77479== by 0x556194: qemu_init (vl.c:3828) ==77479== by 0x40AF9C: main (main.c:48) ==77479== Address 0x583f108 is 0 bytes after a block of size 200 alloc'd ==77479== at 0x483DD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so) ==77479== by 0x4AF8D30: g_malloc0 (in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0.6400.2) ==77479== by 0x844258: type_initialize.part.0 (object.c:306) ==77479== by 0x844D1F: type_initialize (object.c:1029) ==77479== by 0x844D1F: object_class_foreach_tramp (object.c:1016) ==77479== by 0x4AE1057: g_hash_table_foreach (in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0.6400.2) ==77479== by 0x8453A4: object_class_foreach (object.c:1038) ==77479== by 0x8453A4: object_class_get_list (object.c:1095) ==77479== by 0x556194: select_machine (vl.c:2416) ==77479== by 0x556194: qemu_init (vl.c:3828) ==77479== by 0x40AF9C: main (main.c:48) Fixes: 736132e455 ("hw/misc/pca9552: Add generic PCA955xClass") Reported-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 20200629074704.23028-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2020-06-278-0/+585
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/amarkovic/tags/mips-gsoc-queue-jun-27-2020' into staging MIPS + TCG Continuous Benchmarking queue for June 27th, 2020 # gpg: Signature made Sat 27 Jun 2020 20:30:48 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-gsoc-queue-jun-27-2020: MAINTAINERS: Add 'Performance Tools and Tests' subsection scripts/performance: Add topN_callgrind.py script scripts/performance: Add topN_perf.py script MAINTAINERS: Add Loongson-3 maintainer and reviewer hw/intc: Add Loongson LIOINTC support hw/mips: Implement the kvm_type() hook in MachineClass Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * MAINTAINERS: Add 'Performance Tools and Tests' subsectionAleksandar Markovic2020-06-271-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit creates a new 'Miscellaneous' section which hosts a new 'Performance Tools and Tests' subsection. This subsection will contain the the performance scripts and benchmarks written as a part of the 'TCG Continuous Benchmarking' project. Also, it will be a placeholder for follow-ups to this project, if any. Signed-off-by: Ahmed Karaman <ahmedkhaledkaraman@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200626164546.22102-4-ahmedkhaledkaraman@gmail.com>
| * scripts/performance: Add topN_callgrind.py scriptAhmed Karaman2020-06-271-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Python script that prints the top N most executed functions in QEMU using callgrind. Syntax: topN_callgrind.py [-h] [-n] <number of displayed top functions> -- \ <qemu executable> [<qemu executable options>] \ <target executable> [<target execurable options>] [-h] - Print the script arguments help message. [-n] - Specify the number of top functions to print. - If this flag is not specified, the tool defaults to 25. Example of usage: topN_callgrind.py -n 20 -- qemu-arm coulomb_double-arm Example Output: No. Percentage Function Name Source File ---- --------- ------------------ ------------------------------ 1 24.577% 0x00000000082db000 ??? 2 20.467% float64_mul <qemu>/fpu/softfloat.c 3 14.720% float64_sub <qemu>/fpu/softfloat.c 4 13.864% float64_add <qemu>/fpu/softfloat.c 5 4.876% helper_mulsd <qemu>/target/i386/ops_sse.h 6 3.767% helper_subsd <qemu>/target/i386/ops_sse.h 7 3.549% helper_addsd <qemu>/target/i386/ops_sse.h 8 2.185% helper_ucomisd <qemu>/target/i386/ops_sse.h 9 1.667% helper_lookup_tb_ptr <qemu>/include/exec/tb-lookup.h 10 1.662% f64_compare <qemu>/fpu/softfloat.c 11 1.509% helper_lookup_tb_ptr <qemu>/accel/tcg/tcg-runtime.c 12 0.635% helper_lookup_tb_ptr <qemu>/include/exec/exec-all.h 13 0.616% float64_div <qemu>/fpu/softfloat.c 14 0.502% helper_pand_xmm <qemu>/target/i386/ops_sse.h 15 0.502% float64_mul <qemu>/include/fpu/softfloat.h 16 0.476% helper_lookup_tb_ptr <qemu>/target/i386/cpu.h 17 0.437% float64_compare_quiet <qemu>/fpu/softfloat.c 18 0.414% helper_pxor_xmm <qemu>/target/i386/ops_sse.h 19 0.353% round_to_int <qemu>/fpu/softfloat.c 20 0.347% helper_cc_compute_all <qemu>/target/i386/cc_helper.c Signed-off-by: Ahmed Karaman <ahmedkhaledkaraman@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200626164546.22102-3-ahmedkhaledkaraman@gmail.com>
| * scripts/performance: Add topN_perf.py scriptAhmed Karaman2020-06-271-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Syntax: topN_perf.py [-h] [-n] <number of displayed top functions> -- \ <qemu executable> [<qemu executable options>] \ <target executable> [<target execurable options>] [-h] - Print the script arguments help message. [-n] - Specify the number of top functions to print. - If this flag is not specified, the tool defaults to 25. Example of usage: topN_perf.py -n 20 -- qemu-arm coulomb_double-arm Example Output: No. Percentage Name Invoked by ---- ---------- ------------------------- ------------------------- 1 16.25% float64_mul qemu-x86_64 2 12.01% float64_sub qemu-x86_64 3 11.99% float64_add qemu-x86_64 4 5.69% helper_mulsd qemu-x86_64 5 4.68% helper_addsd qemu-x86_64 6 4.43% helper_lookup_tb_ptr qemu-x86_64 7 4.28% helper_subsd qemu-x86_64 8 2.71% f64_compare qemu-x86_64 9 2.71% helper_ucomisd qemu-x86_64 10 1.04% helper_pand_xmm qemu-x86_64 11 0.71% float64_div qemu-x86_64 12 0.63% helper_pxor_xmm qemu-x86_64 13 0.50% 0x00007f7b7004ef95 [JIT] tid 491 14 0.50% 0x00007f7b70044e83 [JIT] tid 491 15 0.36% helper_por_xmm qemu-x86_64 16 0.32% helper_cc_compute_all qemu-x86_64 17 0.30% 0x00007f7b700433f0 [JIT] tid 491 18 0.30% float64_compare_quiet qemu-x86_64 19 0.27% soft_f64_addsub qemu-x86_64 20 0.26% round_to_int qemu-x86_64 Signed-off-by: Ahmed Karaman <ahmedkhaledkaraman@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200626164546.22102-2-ahmedkhaledkaraman@gmail.com>
| * MAINTAINERS: Add Loongson-3 maintainer and reviewerHuacai Chen2020-06-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | Add myself as the maintainer for Loongson-3 virtual platforms, and also add Jiaxun Yang as the reviewer. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1592995531-32600-5-git-send-email-chenhc@lemote.com>
| * hw/intc: Add Loongson LIOINTC supportHuacai Chen2020-06-273-0/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3 has an integrated liointc (Local I/O Interrupt Controller). It is similar to Goldfish interrupt controller, but more powerful (e.g., it can route external interrupt to multi-cores). Documents about Loongson-3's liointc: 1, https://wiki.godson.ac.cn/ip_block:liointc; 2, The "I/O中断" section of Loongson-3's user mannual, part 1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1592995531-32600-3-git-send-email-chenhc@lemote.com>
| * hw/mips: Implement the kvm_type() hook in MachineClassHuacai Chen2020-06-272-0/+37
|/ | | | | | | | | | | | | | | MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we can't create a VZ guest in QEMU because it lacks the kvm_type() hook in MachineClass. This patch add the the kvm_type() hook to support both of the two types. [AM: Added "if defined" guards.] Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <1592995531-32600-2-git-send-email-chenhc@lemote.com>
* Merge remote-tracking branch ↵Peter Maydell2020-06-2629-950/+4417
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging target-arm queue: * hw/arm/aspeed: improve QOM usage * hw/misc/pca9552: trace GPIO change events * target/arm: Implement ARMv8.5-MemTag for system emulation # gpg: Signature made Fri 26 Jun 2020 16:13:27 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200626: (57 commits) target/arm: Enable MTE target/arm: Add allocation tag storage for system mode target/arm: Create tagged ram when MTE is enabled target/arm: Cache the Tagged bit for a page in MemTxAttrs target/arm: Always pass cacheattr to get_phys_addr target/arm: Set PSTATE.TCO on exception entry target/arm: Implement data cache set allocation tags target/arm: Complete TBI clearing for user-only for SVE target/arm: Add mte helpers for sve scatter/gather memory ops target/arm: Handle TBI for sve scalar + int memory ops target/arm: Add mte helpers for sve scalar + int ff/nf loads target/arm: Add mte helpers for sve scalar + int stores target/arm: Add mte helpers for sve scalar + int loads target/arm: Add arm_tlb_bti_gp target/arm: Tidy trans_LD1R_zpri target/arm: Use mte_check1 for sve LD1R target/arm: Use mte_checkN for sve unpredicated stores target/arm: Use mte_checkN for sve unpredicated loads target/arm: Add helper_mte_check_zva target/arm: Implement helper_mte_checkN ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Enable MTERichard Henderson2020-06-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | We now implement all of the components of MTE, without actually supporting any tagged memory. All MTE instructions will work, trivially, so we can enable support. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-46-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add allocation tag storage for system modeRichard Henderson2020-06-261-0/+131
| | | | | | | | | | | | | | | | | | | | | | Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-45-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Create tagged ram when MTE is enabledRichard Henderson2020-06-263-6/+107
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200626033144.790098-44-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Cache the Tagged bit for a page in MemTxAttrsRichard Henderson2020-06-262-3/+50
| | | | | | | | | | | | | | | | | | This "bit" is a particular value of the page's MemAttr. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-43-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Always pass cacheattr to get_phys_addrRichard Henderson2020-06-264-36/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to check the memattr of a page in order to determine whether it is Tagged for MTE. Between Stage1 and Stage2, this becomes simpler if we always collect this data, instead of occasionally being presented with NULL. Use the nonnull attribute to allow the compiler to check that all pointer arguments are non-null. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-42-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Set PSTATE.TCO on exception entryRichard Henderson2020-06-261-0/+3
| | | | | | | | | | | | | | | | | | D1.10 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-41-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement data cache set allocation tagsRichard Henderson2020-06-263-1/+58
| | | | | | | | | | | | | | | | | | This is DC GVA and DC GZVA, and the tag check for DC ZVA. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Complete TBI clearing for user-only for SVERichard Henderson2020-06-263-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number of paths by which the TBI is still intact for user-only in the SVE helpers. Because we currently always set TBI for user-only, we do not need to pass down the actual TBI setting from above, and we can remove the top byte in the inner-most primitives, so that none are forgotten. Moreover, this keeps the "dirty" pointer around at the higher levels, where we need it for any MTE checking. Since the normal case, especially for user-only, goes through RAM, this clearing merely adds two insns per page lookup, which will be completely in the noise. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add mte helpers for sve scatter/gather memory opsRichard Henderson2020-06-263-253/+877
| | | | | | | | | | | | | | | | | | | | | | Because the elements are non-sequential, we cannot eliminate many tests straight away like we can for sequential operations. But we often have the PTE details handy, so we can test for Tagged. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-38-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Handle TBI for sve scalar + int memory opsRichard Henderson2020-06-263-3/+6
| | | | | | | | | | | | | | | | | | We still need to handle tbi for user-only when mte is inactive. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-37-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add mte helpers for sve scalar + int ff/nf loadsRichard Henderson2020-06-263-100/+357
| | | | | | | | | | | | | | | | | | | | Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add mte helpers for sve scalar + int storesRichard Henderson2020-06-263-78/+226
| | | | | | | | | | | | | | | | | | | | Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add mte helpers for sve scalar + int loadsRichard Henderson2020-06-265-98/+385
| | | | | | | | | | | | | | | | | | | | Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add arm_tlb_bti_gpRichard Henderson2020-06-263-2/+15
| | | | | | | | | | | | | | | | | | Introduce an lvalue macro to wrap target_tlb_bit0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Tidy trans_LD1R_zpriRichard Henderson2020-06-261-5/+7
| | | | | | | | | | | | | | | | | | | | Move the variable declarations to the top of the function, but do not create a new label before sve_access_check. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use mte_check1 for sve LD1RRichard Henderson2020-06-261-2/+4
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use mte_checkN for sve unpredicated storesRichard Henderson2020-06-261-28/+33
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use mte_checkN for sve unpredicated loadsRichard Henderson2020-06-261-28/+33
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add helper_mte_check_zvaRichard Henderson2020-06-263-1/+122
| | | | | | | | | | | | | | | | | | | | Use a special helper for DC_ZVA, rather than the more general mte_checkN. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement helper_mte_checkNRichard Henderson2020-06-262-1/+166
| | | | | | | | | | | | | | | | | | Fill out the stub that was added earlier. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement helper_mte_check1Richard Henderson2020-06-262-1/+179
| | | | | | | | | | | | | | | | | | Fill out the stub that was added earlier. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add gen_mte_checkNRichard Henderson2020-06-264-16/+66
| | | | | | | | | | | | | | | | | | | | | | Replace existing uses of check_data_tbi in translate-a64.c that perform multiple logical memory access. Leave the helper blank for now to reduce the patch size. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add gen_mte_check1Richard Henderson2020-06-265-24/+95
| | | | | | | | | | | | | | | | | | | | | | Replace existing uses of check_data_tbi in translate-a64.c that perform a single logical memory access. Leave the helper blank for now to reduce the patch size. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move regime_tcr to internals.hRichard Henderson2020-06-262-9/+9
| | | | | | | | | | | | | | | | | | We will shortly need this in mte_helper.c as well. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move regime_el to internals.hRichard Henderson2020-06-262-36/+36
| | | | | | | | | | | | | | | | | | We will shortly need this in mte_helper.c as well. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the access tag cache flushesRichard Henderson2020-06-261-0/+65
| | | | | | | | | | | | | | | | | | Like the regular data cache flushes, these are nops within qemu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the LDGM, STGM, STZGM instructionsRichard Henderson2020-06-264-8/+153
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Simplify DC_ZVARichard Henderson2020-06-261-70/+26Star
| | | | | | | | | | | | | | | | | | | | Now that we know that the operation is on a single page, we need not loop over pages while probing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Restrict the values of DCZID.BS under TCGRichard Henderson2020-06-261-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We can simplify our DC_ZVA if we recognize that the largest BS that we actually use in system mode is 64. Let us just assert that it fits within TARGET_PAGE_SIZE. For DC_GVA and STZGM, we want to be able to write whole bytes of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the STGP instructionRichard Henderson2020-06-261-3/+26
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement LDG, STG, ST2G instructionsRichard Henderson2020-06-265-5/+386
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Define arm_cpu_do_unaligned_access for user-onlyRichard Henderson2020-06-262-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same code as system mode, so that we generate the same exception + syndrome for the unaligned access. For the moment, if MTE is enabled so that this path is reachable, this would generate a SIGSEGV in the user-only cpu_loop. Decoding the syndrome to produce the proper SIGBUS will be done later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the SUBP instructionRichard Henderson2020-06-261-2/+22
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the GMI instructionRichard Henderson2020-06-261-0/+15
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement the ADDG, SUBG instructionsRichard Henderson2020-06-264-0/+71
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Revise decoding for disas_add_sub_immRichard Henderson2020-06-261-15/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current Arm ARM has adjusted the official decode of "Add/subtract (immediate)" so that the shift field is only bit 22, and bit 23 is part of the op1 field of the parent category "Data processing - immediate". Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-11-richard.henderson@linaro.org Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-03-17 18:39:51 +0100