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* Merge remote-tracking branch ↵Peter Maydell2021-03-101-1/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/thuth-gitlab/tags/pull-request-2021-03-09' into staging * Add some missing gitlab-CI job dependencies * Re-enable "make check SPEED=slow" * Improve the gitlab-pipeline-status script * Clean up inclusing of qtest.h headers * Improve libqos/qgraph documentation * Fix downloading problem in the acceptance tests * Remove deprecated target tilegx * Add new bsd-user maintainers # gpg: Signature made Tue 09 Mar 2021 10:27:29 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2021-03-09: bsd-user: Add new maintainers Remove deprecated target tilegx Acceptance Tests: restore filtering of tests by target arch Acceptance Tests: restore downloading of VM images docs/devel/qgraph: improve qgraph documentation libqos/qgraph: format qgraph comments for sphinx documentation scripts/ci/gitlab-pipeline-status: give more info when pipeline not found scripts/ci/gitlab-pipeline-status: give more information on failures scripts/ci/gitlab-pipeline-status: split utlity function for HTTP GET meson: Re-enable the possibility to run "make check SPEED=slow" docker: OpenSBI build job depends on OpenSBI container docker: EDK2 build job depends on EDK2 container docker: Alpine build job depends on Alpine container qtest: delete superfluous inclusions of qtest.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0Star
| | | | | | | | | | | | | | | | | | | | There are 23 files that include the "sysemu/qtest.h", but they do not use any qtest functions. Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Acked-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210226081414.205946-1-kuhn.chenqun@huawei.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | accel/tcg: Precompute curr_cflags into cpu->tcg_cflagsRichard Henderson2021-03-066-10/+11
| | | | | | | | | | | | | | | | | | The primary motivation is to remove a dozen insns along the fast-path in tb_lookup. As a byproduct, this allows us to completely remove parallel_cpus. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: drop the use of CF_HASH_MASK and rename paramsAlex Bennée2021-03-063-12/+14
| | | | | | | | | | | | | | | | | | | | | | We don't really deal in cf_mask most of the time. The one time it's relevant is when we want to remove an invalidated TB from the QHT lookup. Everywhere else we should be looking up things without CF_INVALID set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: move CF_CLUSTER calculation to curr_cflagsAlex Bennée2021-03-063-9/+8Star
| | | | | | | | | | | | | | | | | | | | There is nothing special about this compile flag that doesn't mean we can't just compute it with curr_cflags() which we should be using when building a new set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: rename tb_lookup__cpu_state and hoist state extractionAlex Bennée2021-03-062-3/+11
|/ | | | | | | | | | Having a function return either and valid TB and some system state seems excessive. It will make the subsequent re-factoring easier if we lookup the current state where we are. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: allow plugin instrumentation to be disable via cflagsAlex Bennée2021-02-183-11/+15
| | | | | | | | | | | | | | | | | | | When icount is enabled and we recompile an MMIO access we end up double counting the instruction execution. To avoid this we introduce the CF_MEMI cflag which only allows memory instrumentation for the next TB (which won't yet have been counted). As this is part of the hashed compile flags we will only execute the generated TB while coming out of a cpu_io_recompile. While we are at it delete the old TODO. We might as well keep the translation handy as it's likely you will repeatedly hit it on each MMIO access. Reported-by: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-21-alex.bennee@linaro.org>
* accel/tcg: remove CF_NOCACHE and special casesAlex Bennée2021-02-181-36/+15Star
| | | | | | | | | | Now we no longer generate CF_NOCACHE blocks we can remove a bunch of the special case handling for them. While we are at it we can remove the unused tb->orig_tb field and save a few bytes on the TB structure. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-20-alex.bennee@linaro.org>
* accel/tcg: re-factor non-RAM execution codeAlex Bennée2021-02-181-15/+15
| | | | | | | | | | There is no real need to use CF_NOCACHE here. As long as the TB isn't linked to other TBs or included in the QHT or jump cache then it will only get executed once. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-19-alex.bennee@linaro.org>
* accel/tcg: cache single instruction TB on pending replay exceptionAlex Bennée2021-02-181-40/+4Star
| | | | | | | | | | | | | | Again there is no reason to jump through the nocache hoops to execute a single instruction block. We do have to add an additional wrinkle to the cpu_handle_interrupt case to ensure we let through a TB where we have specifically disabled icount for the block. As the last user of cpu_exec_nocache we can now remove the function. Further clean-up will follow in subsequent patches. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-18-alex.bennee@linaro.org>
* accel/tcg: actually cache our partial icount TBAlex Bennée2021-02-181-8/+9
| | | | | | | | | | | | | When we exit a block under icount with instructions left to execute we might need a shorter than normal block to take us to the next deterministic event. Instead of creating a throwaway block on demand we use the existing compile flags mechanism to ensure we fetch (or compile and fetch) a block with exactly the number of instructions we need. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-17-alex.bennee@linaro.org>
* target/sh4: Create superh_io_recompile_replay_branchRichard Henderson2021-02-181-12/+0Star
| | | | | | | | | | | Move the code from accel/tcg/translate-all.c to target/sh4/cpu.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-5-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-14-alex.bennee@linaro.org>
* target/mips: Create mips_io_recompile_replay_branchRichard Henderson2021-02-181-10/+2Star
| | | | | | | | | | | Move the code from accel/tcg/translate-all.c to target/mips/cpu.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-4-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-13-alex.bennee@linaro.org>
* accel/tcg: Create io_recompile_replay_branch hookRichard Henderson2021-02-181-4/+13
| | | | | | | | | | | | | | Create a hook in which to split out the mips and sh4 ifdefs from cpu_io_recompile. [AJB: s/stoped/stopped/] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-12-alex.bennee@linaro.org>
* accel/tcg/plugin-gen: fix the call signature for inline callbacksAlex Bennée2021-02-181-21/+11Star
| | | | | | | | | | | | | | | A recent change to the handling of constants in TCG changed the pattern of ops emitted for a constant add. We no longer emit a mov and the constant can be applied directly to the TCG_op_add arguments. This was causing SEGVs when running the insn plugin with arg=inline. Fix this by updating copy_add_i64 to do the right thing while also adding a comment at the top of the append section as an aide memoir if something like this happens again. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Emilio G. Cota <cota@braap.org> Message-Id: <20210213130325.14781-10-alex.bennee@linaro.org>
* exec: Rename guest_{addr,range}_valid to *_untaggedRichard Henderson2021-02-161-1/+2
| | | | | | | | | | | The places that use these are better off using untagged addresses, so do not provide a tagged versions. Rename to make it clear about the address type. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* exec: Use cpu_untagged_addr in g2h; split out g2h_untaggedRichard Henderson2021-02-162-26/+26
| | | | | | | | | | | | | | | | | | | | | | | Use g2h_untagged in contexts that have no cpu, e.g. the binary loaders that operate before the primary cpu is created. As a colollary, target_mmap and friends must use untagged addresses, since they are used by the loaders. Use g2h_untagged on values returned from target_mmap, as the kernel never applies a tag itself. Use g2h_untagged on all pc values. The only current user of tags, aarch64, removes tags from code addresses upon branch, so "pc" is always untagged. Use g2h with the cpu context on hand wherever possible. Use g2h_untagged in lock_user, which will be updated soon. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: Introduce target-specific page data for user-onlyRichard Henderson2021-02-161-0/+28
| | | | | | | | | | | | This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* accel/tcg: Add URL of clang bug to comment about our workaroundPeter Maydell2021-02-111-6/+19
| | | | | | | | | | | | | | | | | | | | | In cpu_exec() we have a longstanding workaround for compilers which do not correctly implement the part of the sigsetjmp()/siglongjmp() spec which requires that local variables which are not changed between the setjmp and the longjmp retain their value. I recently ran across the upstream clang bug report for this; add a link to it to the comment describing the workaround, and generally expand the comment, so that we have a reasonable chance in future of understanding why it's there and determining when we can remove it, assuming clang eventually fixes the bug. Remove the /* buggy compiler */ comments on the #else and #endif: they don't add anything to understanding and are somewhat misleading since they're sandwiching the code path for *non*-buggy compilers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210129130330.30820-1-peter.maydell@linaro.org
* replay: fix replay of the interruptsPavel Dovgalyuk2021-02-081-1/+7
| | | | | | | | | | | | | | | Sometimes interrupt event comes at the same time with the virtual timers. In this case replay tries to proceed the timers, because deadline for them is zero. This patch allows processing interrupts and exceptions by entering the vCPU execution loop, when deadline is zero, but checkpoint associated with virtual timers is not ready to be replayed. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <161216312794.2030770.1709657858900983160.stgit@pasha-ThinkPad-X280> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* accel: replace struct CpusAccel with AccelOpsClassClaudio Fontana2021-02-0510-58/+84
| | | | | | | | | | | | | | | This will allow us to centralize the registration of the cpus.c module accelerator operations (in accel/accel-softmmu.c), and trigger it automatically using object hierarchy lookup from the new accel_init_interfaces() initialization step, depending just on which accelerators are available in the code. Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c, kvm-accel-ops.c, etc, matching the object type names. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-18-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel: extend AccelState and AccelClass to user-modeClaudio Fontana2021-02-052-4/+13
| | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-17-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-053-21/+50
| | | | | | | | | | | | | | | | | | | we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana2021-02-051-1/+2
| | | | | | | | | | | | | commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-15-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-2/+2
| | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-10-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move debug_excp_handler to tcg_opsEduardo Habkost2021-02-051-2/+2
| | | | | | | | | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-8-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-052-6/+7
| | | | | | | | | | | | [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-7-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-6/+6
| | | | | | | | | | | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-6-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-2/+2
| | | | | | | | | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-5-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: split TCG-only code from cpu_exec_realizefnClaudio Fontana2021-02-051-0/+28
| | | | | | | | | | | move away TCG-only code, make it compile only on TCG. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-4-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Restart code generation when we run out of tempsRichard Henderson2021-01-241-1/+14
| | | | | | | | | | | | Some large translation blocks can generate so many unique constants that we run out of temps to hold them. In this case, longjmp back to the start of code generation and restart with a smaller translation block. Buglink: https://bugs.launchpad.net/bugs/1912065 Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Toggle page execution for Apple SiliconRoman Bolshakov2021-01-232-0/+5
| | | | | | | | | | | | | | | Pages can't be both write and executable at the same time on Apple Silicon. macOS provides public API to switch write protection [1] for JIT applications, like TCG. 1. https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon Tested-by: Alexander Graf <agraf@csgraf.de> Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20210113032806.18220-1-r.bolshakov@yadro.com> [rth: Inline the qemu_thread_jit_* functions; drop the MAP_JIT change for a follow-on patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Restrict cpu_io_recompile() from other acceleratorsPhilippe Mathieu-Daudé2021-01-232-0/+3
| | | | | | | | | | As cpu_io_recompile() is only called within TCG accelerator in cputlb.c, declare it locally. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210117164813.4101761-6-f4bug@amsat.org> [rth: Adjust vs changed tb_flush_jmp_cache patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Restrict tb_gen_code() from other acceleratorsPhilippe Mathieu-Daudé2021-01-233-0/+20
| | | | | | | | | tb_gen_code() is only called within TCG accelerator, declare it locally. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210117164813.4101761-4-f4bug@amsat.org> [rth: Adjust vs changed tb_flush_jmp_cache patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move tb_flush_jmp_cache() to cputlb.cRichard Henderson2021-01-232-17/+18
| | | | | | | | Move and make the function static, as the only users are here in cputlb.c. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Make cpu_gen_init() staticPhilippe Mathieu-Daudé2021-01-231-1/+1
| | | | | | | | | | cpu_gen_init() is TCG specific, only used in tcg/translate-all.c. No need to export it to other accelerators, declare it statically. Reviewed-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210117164813.4101761-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: update the cpu running flag in cpu_exec_step_atomicDouglas Crosher2021-01-221-0/+4
| | | | | | | | | | | | | | | The cpu_exec_step_atomic() function is called with the cpu->running clear and proceeds to run target code without setting this flag. If this target code generates an exception then handle_cpu_signal() will unnecessarily abort. For example if atomic code generates a memory protection fault. This patch at least sets and clears this running flag, and adds some assertions to help detect other cases. Signed-off-by: Douglas Crosher <dtc-ubuntu@scieneer.com> Message-Id: <a272c656-f7c5-019d-1cc0-499b8f80f2fc@scieneer.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use tcg_constant_{i32,i64} with tcg pluginsRichard Henderson2021-01-131-27/+22Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-071-7/+9
| | | | | | | | Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfdRichard Henderson2021-01-071-8/+38
| | | | | | | Re-use the 256MiB region handling from alloc_code_gen_buffer_anon, and replace that with the shared file mapping. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Return the TB pointer from the rx region from exit_tbRichard Henderson2021-01-071-14/+21
| | | | | | | | This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Support split-wx for darwin/iOS with vm_remapRichard Henderson2021-01-071-0/+67
| | | | | | | | Cribbed from code posted by Joelle van Dyne <j@getutm.app>, and rearranged to a cleaner structure. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Support split-wx for linux with memfdRichard Henderson2021-01-071-8/+76
| | | | | | | | | We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add --accel tcg,split-wx propertyRichard Henderson2021-01-072-9/+52
| | | | | | | | | Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use Error with alloc_code_gen_bufferRichard Henderson2021-01-071-26/+34
| | | | | | | | | | Report better error messages than just "could not allocate". Let alloc_code_gen_buffer set ctx->code_gen_buffer_size and ctx->code_gen_buffer, and simply return bool. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Make DisasContextBase.tb constRichard Henderson2021-01-071-2/+2
| | | | | | | | | | | | There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson2021-01-071-1/+3
| | | | | | | Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce tcg_splitwx_to_{rx,rw}Richard Henderson2021-01-075-22/+19Star
| | | | | | | | | | | Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour. Begin using the functions in tcg common code only. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add in_code_gen_bufferRichard Henderson2021-01-071-18/+8Star
| | | | | | | Create a function to determine if a pointer is within the buffer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson2021-01-071-1/+1
| | | | | | | | This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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