| Commit message (Expand) | Author | Age | Files | Lines |
* | intel_iommu: Use correct shift for 256 bits qi descriptor | Liu Yi L | 2020-07-22 | 1 | -1/+2 |
* | intel_iommu: add present bit check for pasid table entries | Liu Yi L | 2020-01-06 | 1 | -0/+1 |
* | intel_iommu: TM field should not be in reserved bits | Qi, Yadong | 2019-11-25 | 1 | -3/+10 |
* | intel_iommu: refine SL-PEs reserved fields checking | Qi, Yadong | 2019-11-25 | 1 | -4/+1 |
* | intel_iommu: Drop extended root field | Peter Xu | 2019-04-02 | 1 | -1/+0 |
* | intel_iommu: add scalable-mode option to make scalable mode work | Yi Sun | 2019-03-13 | 1 | -0/+4 |
* | intel_iommu: add 256 bits qi_desc support | Liu, Yi L | 2019-03-13 | 1 | -1/+8 |
* | intel_iommu: scalable mode emulation | Liu, Yi L | 2019-03-13 | 1 | -2/+39 |
* | intel_iommu: dma read/write draining support | Peter Xu | 2018-12-19 | 1 | -0/+3 |
* | intel-iommu: Extend address width to 48 bits | Prasad Singamsetty | 2018-01-18 | 1 | -6/+3 |
* | intel-iommu: Redefine macros to enable supporting 48 bit address width | Prasad Singamsetty | 2018-01-18 | 1 | -8/+26 |
* | intel_iommu: fix iova for pt | Peter Xu | 2017-08-01 | 1 | -1/+0 |
* | intel_iommu: cleanup vtd_{do_}iommu_translate() | Peter Xu | 2017-06-16 | 1 | -0/+1 |
* | intel_iommu: support passthrough (PT) | Peter Xu | 2017-05-25 | 1 | -0/+1 |
* | intel_iommu: enable remote IOTLB | Peter Xu | 2017-04-20 | 1 | -0/+1 |
* | intel_iommu: add "caching-mode" option | Aviv Ben-David | 2017-02-17 | 1 | -0/+1 |
* | intel_iommu: support device iotlb descriptor | Jason Wang | 2017-01-10 | 1 | -2/+11 |
* | intel_iommu: fixing source id during IOTLB hash key calculation | Jason Wang | 2016-11-15 | 1 | -1/+1 |
* | intel_iommu: support all masks in interrupt entry cache invalidation | Radim Krčmář | 2016-07-21 | 1 | -0/+1 |
* | intel_iommu: Add support for Extended Interrupt Mode | Jan Kiszka | 2016-07-21 | 1 | -0/+2 |
* | x86-iommu: introduce IEC notifiers | Peter Xu | 2016-07-21 | 1 | -4/+20 |
* | intel_iommu: Add support for PCI MSI remap | Peter Xu | 2016-07-20 | 1 | -0/+2 |
* | intel_iommu: add IR translation faults defines | Peter Xu | 2016-07-20 | 1 | -0/+13 |
* | intel_iommu: define interrupt remap table addr register | Peter Xu | 2016-07-20 | 1 | -0/+4 |
* | intel_iommu: set IR bit for ECAP register | Peter Xu | 2016-07-20 | 1 | -0/+2 |
* | intel_iommu: allow queued invalidation for IR | Peter Xu | 2016-07-20 | 1 | -0/+2 |
* | intel_iommu: large page support | Jason Wang | 2016-02-06 | 1 | -2/+4 |
* | intel-iommu: add IOTLB using hash table | Le Tan | 2014-08-28 | 1 | -1/+33 |
* | intel-iommu: add context-cache to cache context-entry | Le Tan | 2014-08-28 | 1 | -7/+16 |
* | intel-iommu: add supports for queued invalidation interface | Le Tan | 2014-08-28 | 1 | -6/+21 |
* | intel-iommu: introduce Intel IOMMU (VT-d) emulation | Le Tan | 2014-08-28 | 1 | -0/+333 |