bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work	Peter Maydell	2020-11-02	1	-3/+2
*	arm/gicv3: update virtual irq state after IAR register read	Jeff Kubascik	2020-01-17	1	-0/+3
*	Include hw/irq.h a lot less	Markus Armbruster	2019-08-16	1	-0/+1
*	hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3	Peter Maydell	2019-05-23	1	-2/+2
*	hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}	Peter Maydell	2019-05-23	1	-1/+1
*	target/arm: Introduce arm_hcr_el2_eff	Richard Henderson	2018-12-13	1	-10/+11
*	target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}	Peter Maydell	2018-08-14	1	-9/+10
*	hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQ	Peter Maydell	2018-07-24	1	-1/+1
*	hw/intc/arm_gicv3: Fix APxR<n> register dispatching	Jan Kiszka	2018-05-31	1	-6/+6
*	target/arm: Fetch GICv3 state directly from CPUARMState	Aaron Lindsay	2018-04-26	1	-8/+2
*	hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses	Peter Maydell	2018-03-23	1	-3/+3
*	arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented	Peter Maydell	2017-06-07	1	-5/+1
*	hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1	Peter Maydell	2017-06-02	1	-4/+38
*	hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum	Peter Maydell	2017-06-02	1	-0/+6
*	hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1	Peter Maydell	2017-06-02	1	-1/+1
*	target-arm: Add GICv3CPUState in CPUARMState struct	Vijaya Kumar K	2017-02-28	1	-0/+8
*	tcg: drop global lock during TCG code execution	Jan Kiszka	2017-02-24	1	-0/+3
*	arm_gicv3: Fix broken logic in ELRSR calculation	Peter Maydell	2017-01-27	1	-1/+1
*	hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs	Peter Maydell	2017-01-20	1	-10/+60
*	hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()	Peter Maydell	2017-01-20	1	-0/+49
*	hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR	Peter Maydell	2017-01-20	1	-0/+220
*	hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers	Peter Maydell	2017-01-20	1	-3/+232
*	hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors	Peter Maydell	2017-01-20	1	-0/+239
*	hw/intc/arm_gicv3: Add accessors for ICH_ system registers	Peter Maydell	2017-01-20	1	-0/+477
*	hw/intc/gicv3: Add data fields for virtualization support	Peter Maydell	2017-01-20	1	-0/+13
*	hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset	Peter Maydell	2016-12-27	1	-7/+6
*	hw/intc/arm_gicv3: Fix ICC register tracepoints	Peter Maydell	2016-10-17	1	-8/+15
*	hw/intc/arm_gicv3: Add missing break	Shannon Zhao	2016-06-27	1	-0/+2
*	hw/intc/arm_gicv3: Add IRQ handling CPU interface registers	Peter Maydell	2016-06-17	1	-0/+437
*	hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers	Peter Maydell	2016-06-17	1	-0/+125
*	hw/intc/arm_gicv3: Implement gicv3_cpuif_update()	Peter Maydell	2016-06-17	1	-1/+139
*	hw/intc/arm_gicv3: Implement GICv3 CPU interface registers	Peter Maydell	2016-06-17	1	-0/+646