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path: root/hw/intc/arm_gicv3_cpuif.c
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* hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander2022-11-141-2/+1Star
* Fix 'writeable' typosPeter Maydell2022-06-081-1/+1
* hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell2022-05-191-6/+10
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell2022-05-191-4/+11
* hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell2022-05-191-54/+128
* hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell2022-05-191-1/+1
* hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell2022-05-191-5/+13
* target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson2022-05-051-5/+0Star
* target/arm: Split out cpregs.hRichard Henderson2022-05-051-0/+1
* hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell2022-04-221-1/+5
* hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell2022-04-221-5/+5
* hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell2022-04-221-5/+114
* hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell2022-04-221-24/+40
* hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace eventPeter Maydell2022-03-071-1/+2
* hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.cPhilippe Mathieu-Daudé2021-12-151-9/+1Star
* gicv3: fix ICH_MISR's LRENP computationDamien Hedde2021-12-071-1/+2
* hw/intc/arm_gicv3: fix handling of LPIs in list registersPeter Maydell2021-11-291-3/+2Star
* hw/intc/arm_gicv3: Add new gicv3_intid_is_special() functionPeter Maydell2021-11-261-2/+2
* hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela2021-09-201-2/+3
* hw/intc: GICv3 redistributor ITS processingShashi Mallela2021-09-131-2/+5
* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_writeRicardo Koller2021-07-091-2/+2
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writesJean-Philippe Brucker2021-06-151-1/+4
* hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logicPeter Maydell2021-05-251-16/+32
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts workPeter Maydell2020-11-021-3/+2Star
* arm/gicv3: update virtual irq state after IAR register readJeff Kubascik2020-01-171-0/+3
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-161-0/+1
* hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3Peter Maydell2019-05-231-2/+2
* hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}Peter Maydell2019-05-231-1/+1
* target/arm: Introduce arm_hcr_el2_effRichard Henderson2018-12-131-10/+11
* target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}Peter Maydell2018-08-141-9/+10
* hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQPeter Maydell2018-07-241-1/+1
* hw/intc/arm_gicv3: Fix APxR<n> register dispatchingJan Kiszka2018-05-311-6/+6
* target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay2018-04-261-8/+2Star
* hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accessesPeter Maydell2018-03-231-3/+3
* arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implementedPeter Maydell2017-06-071-5/+1Star
* hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1Peter Maydell2017-06-021-4/+38
* hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimumPeter Maydell2017-06-021-0/+6
* hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1Peter Maydell2017-06-021-1/+1
* target-arm: Add GICv3CPUState in CPUARMState structVijaya Kumar K2017-02-281-0/+8
* tcg: drop global lock during TCG code executionJan Kiszka2017-02-241-0/+3
* arm_gicv3: Fix broken logic in ELRSR calculationPeter Maydell2017-01-271-1/+1
* hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regsPeter Maydell2017-01-201-10/+60
* hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()Peter Maydell2017-01-201-0/+49
* hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IARPeter Maydell2017-01-201-0/+220
* hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registersPeter Maydell2017-01-201-3/+232
* hw/intc/arm_gicv3: Implement ICV_ registers which are just accessorsPeter Maydell2017-01-201-0/+239
* hw/intc/arm_gicv3: Add accessors for ICH_ system registersPeter Maydell2017-01-201-0/+477
* hw/intc/gicv3: Add data fields for virtualization supportPeter Maydell2017-01-201-0/+13
* hw/intc/arm_gicv3: Remove incorrect usage of fieldoffsetPeter Maydell2016-12-271-7/+6Star
* hw/intc/arm_gicv3: Fix ICC register tracepointsPeter Maydell2016-10-171-8/+15
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