| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 | Peter Maydell | 2019-06-17 | 1 | -1/+7 |
| * | hw/intc/arm_gicv3: Fix decoding of ID register range | Peter Maydell | 2019-06-17 | 1 | -2/+2 |
| * | hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR | Amol Surati | 2018-06-22 | 1 | -1/+2 |
| * | hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI | Peter Maydell | 2018-01-11 | 1 | -0/+13 |
| * | hw/intc/arm_gicv3: Fix compilation with simple trace backend | Peter Maydell | 2016-06-20 | 1 | -0/+1 |
| * | hw/intc/arm_gicv3: Implement gicv3_set_irq() | Peter Maydell | 2016-06-17 | 1 | -0/+21 |
| * | hw/intc/arm_gicv3: Implement GICv3 distributor registers | Shlomo Pongratz | 2016-06-17 | 1 | -0/+858 |
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index : bwlp/qemu.git | |
| Experimental fork of QEMU with video encoding patches | OpenSLX |
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