bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix 'writeable' typos	Peter Maydell	2022-06-08	1	-1/+1
*	hw/intc/arm_gicv3: Update ID and feature registers for GICv4	Peter Maydell	2022-04-22	1	-3/+4
*	hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers	Peter Maydell	2022-04-22	1	-1/+1
*	hw/intc/arm_gicv3: Fix missing spaces in error log messages	Peter Maydell	2022-03-07	1	-2/+2
*	hw/intc: GICv3 ITS Feature enablement	Shashi Mallela	2021-09-13	1	-1/+4
*	hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans	Philippe Mathieu-Daudé	2021-09-01	1	-95/+106
*	hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix	Philippe Mathieu-Daudé	2021-09-01	1	-6/+6
*	hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1	Peter Maydell	2019-06-17	1	-1/+7
*	hw/intc/arm_gicv3: Fix decoding of ID register range	Peter Maydell	2019-06-17	1	-2/+2
*	hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR	Amol Surati	2018-06-22	1	-1/+2
*	hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI	Peter Maydell	2018-01-11	1	-0/+13
*	hw/intc/arm_gicv3: Fix compilation with simple trace backend	Peter Maydell	2016-06-20	1	-0/+1
*	hw/intc/arm_gicv3: Implement gicv3_set_irq()	Peter Maydell	2016-06-17	1	-0/+21
*	hw/intc/arm_gicv3: Implement GICv3 distributor registers	Shlomo Pongratz	2016-06-17	1	-0/+858