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path: root/hw/riscv/opentitan.c
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* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-24/+57
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-1/+2
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-0/+1
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-42/+42
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-5/+2Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-101-4/+2Star
* hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-15/+14Star
* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-2/+23
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-2/+12
* riscv/opentitan: Fix the ROM sizeAlistair Francis2020-06-191-1/+2
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-2/+1Star
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-151-4/+2Star
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-2/+1Star
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-3/+2Star
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-031-0/+184