bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	hw/riscv: opentitan: Expose the resetvec as a SoC property	Alistair Francis	2022-09-26	1	-1/+7
*	hw/riscv: opentitan: Fixup resetvec	Alistair Francis	2022-09-26	1	-1/+1
*	hw/riscv: opentitan: bump opentitan version	Wilfred Mallawa	2022-09-07	1	-4/+8
*	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI	2022-05-24	1	-1/+1
*	riscv: opentitan: Connect opentitan SPI Host	Wilfred Mallawa	2022-04-22	1	-4/+32
*	hw: riscv: opentitan: fixup SPI addresses	Wilfred Mallawa	2022-03-03	1	-3/+9
*	riscv: opentitan: fixup plic stride len	Wilfred Mallawa	2022-01-21	1	-1/+1
*	hw/riscv: Use error_fatal for SoC realisation	Alistair Francis	2022-01-08	1	-1/+1
*	hw/riscv: opentitan: Fixup the PLIC context addresses	Alistair Francis	2021-10-28	1	-2/+2
*	hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id	Bin Meng	2021-10-22	1	-4/+12
*	hw/riscv: opentitan: Update to the latest build	Alistair Francis	2021-10-22	1	-5/+17
*	hw/riscv: opentitan: Correct the USB Dev address	Alistair Francis	2021-09-21	1	-1/+1
*	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	Alistair Francis	2021-09-20	1	-0/+3
*	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis	2021-09-20	1	-0/+8
*	hw/riscv: opentitan: Add the flash alias	Alistair Francis	2021-07-15	1	-0/+6
*	hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri	Alistair Francis	2021-07-15	1	-0/+3
*	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	Alistair Francis	2021-06-24	1	-3/+11
*	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner	2021-05-11	1	-1/+1
*	hw/opentitan: Update the interrupt layout	Alistair Francis	2021-05-11	1	-4/+4
*	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth	2021-05-02	1	-1/+0
*	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng	2021-03-04	1	-6/+3
*	riscv/opentitan: Update the OpenTitan memory layout	Alistair Francis	2020-12-18	1	-24/+57
*	hw/riscv: Load the kernel after the firmware	Alistair Francis	2020-10-22	1	-1/+2
*	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng	2020-09-10	1	-0/+1
*	opentitan: Rename memmap enum constants	Eduardo Habkost	2020-08-27	1	-42/+42
*	error: Eliminate error_propagate() with Coccinelle, part 1	Markus Armbruster	2020-07-10	1	-5/+2
*	qom: Put name parameter before value / visitor parameter	Markus Armbruster	2020-07-10	1	-2/+2
*	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster	2020-07-10	1	-4/+2
*	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	2020-06-19	1	-15/+14
*	riscv/opentitan: Connect the UART device	Alistair Francis	2020-06-19	1	-2/+23
*	riscv/opentitan: Connect the PLIC device	Alistair Francis	2020-06-19	1	-2/+12
*	riscv/opentitan: Fix the ROM size	Alistair Francis	2020-06-19	1	-1/+2
*	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster	2020-06-15	1	-2/+1
*	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster	2020-06-15	1	-4/+2
*	qom: Less verbose object_initialize_child()	Markus Armbruster	2020-06-15	1	-2/+1
*	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster	2020-06-15	1	-3/+2
*	riscv: Initial commit of OpenTitan machine	Alistair Francis	2020-06-03	1	-0/+184