| Commit message (Expand) | Author | Age | Files | Lines |
* | sifive_u: Register "start-in-flash" as class property | Eduardo Habkost | 2020-09-22 | 1 | -8/+8 |
* | sifive_u: Rename memmap enum constants | Eduardo Habkost | 2020-09-18 | 1 | -78/+78 |
* | hw/riscv: Move sifive_uart model to hw/char | Bin Meng | 2020-09-10 | 1 | -1/+1 |
* | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng | 2020-09-10 | 1 | -1/+1 |
* | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng | 2020-09-10 | 1 | -1/+1 |
* | hw/riscv: sifive_u: Connect a DMA controller | Bin Meng | 2020-09-10 | 1 | -0/+30 |
* | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng | 2020-09-10 | 1 | -1/+2 |
* | target/riscv: cpu: Set reset vector based on the configured property value | Bin Meng | 2020-09-10 | 1 | -0/+2 |
* | hw/riscv: Allow creating multiple instances of PLIC | Anup Patel | 2020-08-25 | 1 | -1/+1 |
* | hw/riscv: Allow creating multiple instances of CLINT | Anup Patel | 2020-08-25 | 1 | -1/+1 |
* | hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u | Bin Meng | 2020-08-22 | 1 | -2/+2 |
* | hw/riscv: sifive_u: Add a dummy L2 cache controller device | Bin Meng | 2020-08-22 | 1 | -0/+22 |
* | hw: Mark nd_table[] misuse in realize methods FIXME | Markus Armbruster | 2020-07-21 | 1 | -0/+1 |
* | hw/riscv: Modify MROM size to end at 0x10000 | Bin Meng | 2020-07-14 | 1 | -1/+1 |
* | RISC-V: Support 64 bit start address | Atish Patra | 2020-07-14 | 1 | -1/+5 |
* | riscv: Add opensbi firmware dynamic support | Atish Patra | 2020-07-14 | 1 | -5/+15 |
* | RISC-V: Copy the fdt in dram instead of ROM | Atish Patra | 2020-07-14 | 1 | -15/+13 |
* | riscv: Unify Qemu's reset vector code path | Atish Patra | 2020-07-14 | 1 | -1/+0 |
* | error: Eliminate error_propagate() with Coccinelle, part 1 | Markus Armbruster | 2020-07-10 | 1 | -3/+1 |
* | qom: Put name parameter before value / visitor parameter | Markus Armbruster | 2020-07-10 | 1 | -3/+3 |
* | qdev: Use returned bool to check for qdev_realize() etc. failure | Markus Armbruster | 2020-07-10 | 1 | -2/+1 |
* | riscv/sifive_u: Fix sifive_u_soc_realize() error API violations | Markus Armbruster | 2020-07-02 | 1 | -3/+9 |
* | hw/riscv: sifive_u: Add a dummy DDR memory controller device | Bin Meng | 2020-06-19 | 1 | -0/+4 |
* | hw/riscv: sifive_u: Sort the SoC memmap table entries | Bin Meng | 2020-06-19 | 1 | -2/+2 |
* | hw/riscv: sifive_u: Support different boot source per MSEL pin state | Bin Meng | 2020-06-19 | 1 | -8/+31 |
* | hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 | Bin Meng | 2020-06-19 | 1 | -3/+3 |
* | hw/riscv: sifive_u: Add a new property msel for MSEL pin state | Bin Meng | 2020-06-19 | 1 | -0/+7 |
* | hw/riscv: sifive_u: Rename serial property get/set functions to a generic name | Bin Meng | 2020-06-19 | 1 | -6/+8 |
* | hw/riscv: sifive_u: Add reset functionality | Bin Meng | 2020-06-19 | 1 | -1/+23 |
* | hw/riscv: sifive_u: Hook a GPIO controller | Bin Meng | 2020-06-19 | 1 | -2/+41 |
* | hw/riscv: sifive_u: Generate device tree node for OTP | Bin Meng | 2020-06-19 | 1 | -0/+11 |
* | hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit | Bin Meng | 2020-06-19 | 1 | -6/+1 |
* | qdev: Convert bus-less devices to qdev_realize() with Coccinelle | Markus Armbruster | 2020-06-15 | 1 | -6/+3 |
* | sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 | Markus Armbruster | 2020-06-15 | 1 | -19/+12 |
* | qom: Less verbose object_initialize_child() | Markus Armbruster | 2020-06-15 | 1 | -9/+3 |
* | riscv: Fix to put "riscv.hart_array" devices on sysbus | Markus Armbruster | 2020-06-15 | 1 | -8/+6 |
* | hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions | Bin Meng | 2020-06-03 | 1 | -12/+12 |
* | qom: Drop parameter @errp of object_property_add() & friends | Markus Armbruster | 2020-05-15 | 1 | -4/+6 |
* | qom: Drop object_property_set_description() parameter @errp | Markus Armbruster | 2020-05-15 | 1 | -3/+2 |
* | hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() | Anup Patel | 2020-04-29 | 1 | -1/+1 |
* | hw/riscv: Generate correct "mmu-type" for 32-bit machines | Bin Meng | 2020-04-29 | 1 | -0/+4 |
* | riscv/sifive_u: Add a serial property to the sifive_u machine | Bin Meng | 2020-04-29 | 1 | -0/+20 |
* | riscv/sifive_u: Add a serial property to the sifive_u SoC | Alistair Francis | 2020-04-29 | 1 | -1/+7 |
* | riscv/sifive_u: Fix up file ordering | Alistair Francis | 2020-04-29 | 1 | -54/+54 |
* | various: Remove suspicious '\' character outside of #define in C code | Philippe Mathieu-Daudé | 2020-04-29 | 1 | -1/+1 |
* | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell | 2020-03-17 | 1 | -1/+1 |
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| * | hw/riscv: Let devices own the MemoryRegion they create | Philippe Mathieu-Daudé | 2020-03-17 | 1 | -1/+1 |
* | | riscv: sifive_u: Update BIOS_FILENAME for 32-bit | Bin Meng | 2020-03-17 | 1 | -1/+5 |
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* | hw/riscv: Provide rdtime callback for TCG in CLINT emulation | Anup Patel | 2020-02-27 | 1 | -1/+1 |
* | riscv/sifive_u: fix a memory leak in soc_realize() | Pan Nengyuan | 2020-01-16 | 1 | -0/+1 |