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path: root/hw/riscv/sifive_uart.c
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* chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé2020-01-081-1/+1
* riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng2019-09-171-1/+0Star
* riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng2019-09-171-4/+5
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-0/+1
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-161-0/+1
* riscv: sifive_uart: Generate TX interruptBin Meng2019-03-191-1/+3
* sifive_uart: Implement interrupt pending registerNathaniel Graff2018-12-201-5/+19
* SiFive RISC-V UART DeviceMichael Clark2018-03-061-0/+176