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path: root/hw/riscv/spike.c
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* qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0Star
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-4/+4
* hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-181-21/+24
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+2
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-3/+8
* hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-74/+158
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: spike: Change the default bios to use generic platform imageBin Meng2020-08-221-2/+7
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-3/+10
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+6
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-38/+3Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-151-4/+3Star
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-2/+2
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-217/+0Star
* hw/riscv/spike: Allow more than one CPUsAnup Patel2020-04-291-1/+1
* hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel2020-04-291-1/+23
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-291-0/+4
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell2020-03-031-3/+6
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| * hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-3/+6
* | hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé2020-02-281-1/+1
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* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-3/+3
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-2/+0Star
* riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-171-1/+0Star
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-051-0/+3
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-17/+4Star
* riscv: spike: Add a generic spike machineAlistair Francis2019-05-241-1/+105
* riscv: Ensure the kernel start address is correctly castAlistair Francis2019-02-121-1/+1
* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-051-1/+1
* riscv: spike: Fix memory leak in the board initAlistair Francis2018-11-081-3/+3
* RISC-V: Don't add NULL bootargs to device-treeMichael Clark2018-10-171-2/+4
* Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...Peter Maydell2018-09-251-1/+1
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| * Drop "qemu:" prefix from error_report() argumentsMao Zhongyi2018-09-241-1/+1
* | hw/riscv/spike: Set the soc device tree node as a simple-busAlistair Francis2018-09-051-1/+1
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* spike: Fix crash when introspecting the deviceAlistair Francis2018-07-191-6/+4Star
* RISC-V: Mark ROM read-only after copying in codeMichael Clark2018-05-061-28/+41
* RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark2018-05-061-1/+1
* RISC-V: Remove unused class definitionsMichael Clark2018-05-061-20/+0Star
* RISC-V: Remove identity_translate from load_elfMichael Clark2018-05-061-6/+1Star
* RISC-V: Replace hardcoded constants with enum valuesMichael Clark2018-05-061-2/+4
* Change references to serial_hds[] to serial_hd()Peter Maydell2018-04-261-2/+2
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