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path: root/hw/riscv/virt.c
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* hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra2022-06-101-10/+18
* hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel2022-05-241-13/+12Star
* hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI2022-05-241-1/+1
* hw/riscv: Enable TPM backendsAlistair Francis2022-04-291-0/+4
* hw/riscv: virt: Add device plug supportAlistair Francis2022-04-291-0/+35
* hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis2022-04-291-0/+19
* hw/riscv: virt: Create a platform busAlistair Francis2022-04-291-19/+49
* hw/riscv: virt: Add a machine done notifierAlistair Francis2022-04-291-90/+101
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel2022-04-221-2/+8
* hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer2022-04-221-4/+10
* hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel2022-03-031-0/+10
* hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2022-03-031-81/+358
* hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2022-03-031-53/+238
* hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel2022-02-161-2/+11
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-25/+58
* hw/riscv: virt: Use the PLIC config helper functionAlistair Francis2021-10-281-19/+1Star
* hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+1
* hw/riscv: virt: Use machine->ram as the system memoryMingwang Li2021-10-211-4/+2Star
* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-201-1/+112
* hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-201-200/+327
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-201-5/+9
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-1/+1
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-1/+1
* hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell2021-09-011-13/+20
* hw/riscv: virt: Move flash node to rootBin Meng2021-09-011-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0Star
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2Star
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-2/+5
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* hw/riscv: allow ramfb on virtAsherah Connor2021-03-231-0/+3
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-231-0/+30
* hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-10/+10
* hw/riscv: virt: Map high mmio for PCIeBin Meng2021-03-041-2/+33
* hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng2021-03-041-0/+10
* hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng2021-03-041-7/+7
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-4/+5
* hw/riscv: virt: Remove compile time XLEN checksAlistair Francis2020-12-181-15/+17
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+1
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2Star
* hw/riscv: virt: Allow passing custom DTBAnup Patel2020-11-031-7/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-3/+8
* hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
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