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* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-152-2/+2
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
* hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis2021-10-281-2/+2
* hw/riscv: virt: Use the PLIC config helper functionAlistair Francis2021-10-281-19/+1Star
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1Star
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1Star
* hw/riscv: boot: Add a PLIC config string functionAlistair Francis2021-10-281-0/+25
* hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+1
* hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng2021-10-221-16/+20
* hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-5/+17
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-1/+1
* hw/riscv: virt: Use machine->ram as the system memoryMingwang Li2021-10-211-4/+2Star
* hw/riscv: shakti_c: Mark as not user creatableAlistair Francis2021-10-071-0/+7
* hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-201-1/+112
* hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-201-200/+327
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-206-24/+44
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-207-12/+12
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-202-1/+55
* hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+3
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-205-5/+6
* hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+8
* hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell2021-09-011-13/+20
* hw/riscv: virt: Move flash node to rootBin Meng2021-09-011-1/+1
* hw/char: Add config for shakti uartVijai Kumar K2021-09-011-4/+1Star
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-264-4/+0Star
* hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé2021-07-202-1/+6
* hw/riscv/boot: Check the error of fdt_pack()Alistair Francis2021-07-151-2/+4
* hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-151-0/+6
* hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-151-0/+3
* hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
* hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
* hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis2021-06-241-3/+11
* hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng2021-06-081-3/+78
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-083-12/+6Star
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-082-2/+10
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-083-3/+15
* hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-2/+5
* hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-3/+3
* hw/riscv: Fix OT IBEX reset vectorAlexander Wagner2021-05-111-1/+1
* hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis2021-05-111-0/+1
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-4/+4
* hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K2021-05-111-0/+8
* riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-113-0/+184
* hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng2021-05-111-1/+1
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