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* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-054-4/+4
* sifive_uart: Implement interrupt pending registerNathaniel Graff2018-12-201-5/+19
* RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark2018-12-202-6/+4Star
* RISC-V: Fix PLIC pending bitfield readsMichael Clark2018-12-201-1/+1
* RISC-V: Fix CLINT timecmp low 32-bit writesMichael Clark2018-12-201-4/+4
* sifive_u: Set 'clock-frequency' DT property for SiFive UARTAnup Patel2018-12-201-0/+2
* sifive_u: Add clock DT node for GEM ethernetAnup Patel2018-12-201-1/+17
* hw/riscv/virt: Connect the gpex PCIeAlistair Francis2018-12-201-1/+130
* hw/riscv/virt: Adjust memory layout spacingAlistair Francis2018-12-201-8/+8
* hw/riscv/virt: Free the test device tree node nameAlistair Francis2018-11-141-0/+1
* riscv: spike: Fix memory leak in the board initAlistair Francis2018-11-081-3/+3
* RISC-V: Don't add NULL bootargs to device-treeMichael Clark2018-10-173-4/+10
* RISC-V: Add missing free for plic_hart_configMichael Clark2018-10-171-0/+2
* RISC-V: Allow setting and clearing multiple irqsMichael Clark2018-10-172-6/+6
* Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...Peter Maydell2018-09-254-5/+5
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| * Drop "qemu:" prefix from error_report() argumentsMao Zhongyi2018-09-244-5/+5
* | hw/riscv/spike: Set the soc device tree node as a simple-busAlistair Francis2018-09-051-1/+1
* | hw/riscv/virtio: Set the soc device tree node as a simple-busAlistair Francis2018-09-051-1/+1
* | RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark2018-09-041-27/+22Star
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* spike: Fix crash when introspecting the deviceAlistair Francis2018-07-191-6/+4Star
* riscv_hart: Fix crash when introspecting the deviceAlistair Francis2018-07-191-4/+3Star
* virt: Fix crash when introspecting the deviceAlistair Francis2018-07-191-3/+2Star
* sifive_u: Fix crash when introspecting the deviceAlistair Francis2018-07-191-8/+7Star
* sifive_e: Fix crash when introspecting the deviceAlistair Francis2018-07-191-6/+6
* hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis2018-07-061-0/+50
* hw/riscv/sifive_u: Move the uart device tree node under /soc/Alistair Francis2018-07-061-1/+1
* hw/riscv/sifive_u: Set the interrupt controller number of interruptsAlistair Francis2018-07-061-1/+1
* hw/riscv/sifive_u: Set the soc device tree node as a simple-busAlistair Francis2018-07-061-1/+1
* hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis2018-07-064-11/+9Star
* hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis2018-07-061-25/+69
* hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis2018-07-061-22/+65
* hw/riscv: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé2018-07-021-1/+2
* hw: Do not include "exec/address-spaces.h" if it is not necessaryPhilippe Mathieu-Daudé2018-06-011-1/+0Star
* Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-...Peter Maydell2018-05-101-4/+8
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| * riscv: htif: increase the priority of the htif subregionKONRAD Frederic2018-05-081-2/+3
| * riscv: spike: allow base == 0KONRAD Frederic2018-05-081-2/+5
* | RISC-V: Mark ROM read-only after copying in codeMichael Clark2018-05-064-82/+101
* | RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark2018-05-064-4/+4
* | RISC-V: Remove unused class definitionsMichael Clark2018-05-065-101/+0Star
* | RISC-V: Remove identity_translate from load_elfMichael Clark2018-05-064-24/+4Star
* | RISC-V: Use ROM base address and size from memmapMichael Clark2018-05-061-2/+2
* | RISC-V: Make virt board description match spikeMichael Clark2018-05-061-1/+1
* | RISC-V: Replace hardcoded constants with enum valuesMichael Clark2018-05-064-12/+15
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* Change references to serial_hds[] to serial_hd()Peter Maydell2018-04-264-7/+7
* RISC-V Build InfrastructureMichael Clark2018-03-061-0/+11
* SiFive Freedom U Series RISC-V MachineMichael Clark2018-03-061-0/+339
* SiFive Freedom E Series RISC-V MachineMichael Clark2018-03-061-0/+234
* SiFive RISC-V PRCI BlockMichael Clark2018-03-061-0/+89
* SiFive RISC-V UART DeviceMichael Clark2018-03-061-0/+176
* RISC-V VirtIO MachineMichael Clark2018-03-061-0/+420
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