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* hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis2022-04-291-0/+19
* hw/riscv: virt: Create a platform busAlistair Francis2022-04-292-19/+50
* hw/riscv: virt: Add a machine done notifierAlistair Francis2022-04-291-90/+101
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-294-4/+4
* hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng2022-04-291-2/+3
* hw/riscv: boot: Support 64bit fdt address.Dylan Jhong2022-04-221-5/+7
* hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel2022-04-221-2/+8
* hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer2022-04-221-4/+10
* riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa2022-04-221-4/+32
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
* hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa2022-03-031-3/+9
* hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel2022-03-031-0/+10
* hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2022-03-032-81/+359
* hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2022-03-032-53/+239
* hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel2022-02-161-2/+11
* hw/riscv: Remove macros for ELF BIOS image namesAnup Patel2022-01-211-2/+2
* hw/riscv: spike: Allow using binary firmware as biosAnup Patel2022-01-211-16/+25
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-212-26/+73
* riscv: opentitan: fixup plic stride lenWilfred Mallawa2022-01-211-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-084-4/+4
* hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke2021-12-201-3/+10
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-152-2/+2
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
* hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis2021-10-281-2/+2
* hw/riscv: virt: Use the PLIC config helper functionAlistair Francis2021-10-281-19/+1Star
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1Star
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1Star
* hw/riscv: boot: Add a PLIC config string functionAlistair Francis2021-10-281-0/+25
* hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+1
* hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng2021-10-221-16/+20
* hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-5/+17
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-1/+1
* hw/riscv: virt: Use machine->ram as the system memoryMingwang Li2021-10-211-4/+2Star
* hw/riscv: shakti_c: Mark as not user creatableAlistair Francis2021-10-071-0/+7
* hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-201-1/+112
* hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-201-200/+327
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-206-24/+44
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-207-12/+12
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-202-1/+55
* hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+3
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-205-5/+6
* hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+8
* hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell2021-09-011-13/+20
* hw/riscv: virt: Move flash node to rootBin Meng2021-09-011-1/+1
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