| Commit message (Expand) | Author | Age | Files | Lines |
* | hw/riscv: Enable TPM backends | Alistair Francis | 2022-04-29 | 2 | -0/+5 |
* | hw/riscv: virt: Add device plug support | Alistair Francis | 2022-04-29 | 1 | -0/+35 |
* | hw/riscv: virt: Add support for generating platform FDT entries | Alistair Francis | 2022-04-29 | 1 | -0/+19 |
* | hw/riscv: virt: Create a platform bus | Alistair Francis | 2022-04-29 | 2 | -19/+50 |
* | hw/riscv: virt: Add a machine done notifier | Alistair Francis | 2022-04-29 | 1 | -90/+101 |
* | hw/riscv: Don't add empty bootargs to device tree | Bin Meng | 2022-04-29 | 4 | -4/+4 |
* | hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally | Bin Meng | 2022-04-29 | 1 | -2/+3 |
* | hw/riscv: boot: Support 64bit fdt address. | Dylan Jhong | 2022-04-22 | 1 | -5/+7 |
* | hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled | Niklas Cassel | 2022-04-22 | 1 | -2/+8 |
* | hw/riscv: virt: Exit if the user provided -bios in combination with KVM | Ralf Ramsauer | 2022-04-22 | 1 | -4/+10 |
* | riscv: opentitan: Connect opentitan SPI Host | Wilfred Mallawa | 2022-04-22 | 1 | -4/+32 |
* | Remove qemu-common.h include from most units | Marc-André Lureau | 2022-04-06 | 1 | -1/+0 |
* | hw: riscv: opentitan: fixup SPI addresses | Wilfred Mallawa | 2022-03-03 | 1 | -3/+9 |
* | hw/riscv: virt: Increase maximum number of allowed CPUs | Anup Patel | 2022-03-03 | 1 | -0/+10 |
* | hw/riscv: virt: Add optional AIA IMSIC support to virt machine | Anup Patel | 2022-03-03 | 2 | -81/+359 |
* | hw/riscv: virt: Add optional AIA APLIC support to virt machine | Anup Patel | 2022-03-03 | 2 | -53/+239 |
* | hw/riscv: virt: Use AIA INTC compatible string when available | Anup Patel | 2022-02-16 | 1 | -2/+11 |
* | hw/riscv: Remove macros for ELF BIOS image names | Anup Patel | 2022-01-21 | 1 | -2/+2 |
* | hw/riscv: spike: Allow using binary firmware as bios | Anup Patel | 2022-01-21 | 1 | -16/+25 |
* | target/riscv: Support start kernel directly by KVM | Yifei Jiang | 2022-01-21 | 2 | -26/+73 |
* | riscv: opentitan: fixup plic stride len | Wilfred Mallawa | 2022-01-21 | 1 | -1/+1 |
* | hw/riscv: Use error_fatal for SoC realisation | Alistair Francis | 2022-01-08 | 4 | -4/+4 |
* | hw/riscv: Use load address rather than entry point for fw_dynamic next_addr | Jessica Clarke | 2021-12-20 | 1 | -3/+10 |
* | hw: Replace trivial drive_get_next() by drive_get() | Markus Armbruster | 2021-12-15 | 2 | -2/+2 |
* | hw/sd/ssi-sd: Do not create SD card within controller's realize | Markus Armbruster | 2021-12-15 | 1 | -1/+12 |
* | hw/riscv: opentitan: Fixup the PLIC context addresses | Alistair Francis | 2021-10-28 | 1 | -2/+2 |
* | hw/riscv: virt: Use the PLIC config helper function | Alistair Francis | 2021-10-28 | 1 | -19/+1 |
* | hw/riscv: microchip_pfsoc: Use the PLIC config helper function | Alistair Francis | 2021-10-28 | 1 | -13/+1 |
* | hw/riscv: sifive_u: Use the PLIC config helper function | Alistair Francis | 2021-10-28 | 1 | -13/+1 |
* | hw/riscv: boot: Add a PLIC config string function | Alistair Francis | 2021-10-28 | 1 | -0/+25 |
* | hw/riscv: virt: Don't use a macro for the PLIC configuration | Alistair Francis | 2021-10-28 | 1 | -1/+1 |
* | hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 2021-10-22 | 1 | -4/+2 |
* | hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 2021-10-22 | 1 | -4/+2 |
* | hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 2021-10-22 | 1 | -4/+12 |
* | hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 2021-10-22 | 1 | -4/+2 |
* | hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 2021-10-22 | 1 | -4/+12 |
* | hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra... | Bin Meng | 2021-10-22 | 1 | -16/+20 |
* | hw/riscv: opentitan: Update to the latest build | Alistair Francis | 2021-10-22 | 1 | -5/+17 |
* | target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl | Richard Henderson | 2021-10-21 | 1 | -1/+1 |
* | hw/riscv: virt: Use machine->ram as the system memory | Mingwang Li | 2021-10-21 | 1 | -4/+2 |
* | hw/riscv: shakti_c: Mark as not user creatable | Alistair Francis | 2021-10-07 | 1 | -0/+7 |
* | hw/riscv: opentitan: Correct the USB Dev address | Alistair Francis | 2021-09-21 | 1 | -1/+1 |
* | hw/riscv: virt: Add optional ACLINT support to virt machine | Anup Patel | 2021-09-20 | 1 | -1/+112 |
* | hw/riscv: virt: Re-factor FDT generation | Anup Patel | 2021-09-20 | 1 | -200/+327 |
* | hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT | Anup Patel | 2021-09-20 | 6 | -24/+44 |
* | hw/intc: Rename sifive_clint sources to riscv_aclint sources | Anup Patel | 2021-09-20 | 7 | -12/+12 |
* | sifive_u: Connect the SiFive PWM device | Alistair Francis | 2021-09-20 | 2 | -1/+55 |
* | hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines | Alistair Francis | 2021-09-20 | 1 | -0/+3 |
* | hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines | Alistair Francis | 2021-09-20 | 5 | -5/+6 |
* | hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines | Alistair Francis | 2021-09-20 | 1 | -0/+8 |