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* hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis2020-07-021-1/+1
* riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke2020-07-021-1/+2
* riscv: plic: Honour source prioritiesJessica Clarke2020-07-021-5/+12
* riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster2020-07-021-9/+5Star
* riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster2020-07-021-3/+9
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+4
* hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng2020-06-191-2/+2
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-8/+31
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-192-7/+9
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+7
* hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng2020-06-191-6/+8
* hw/riscv: sifive_u: Add reset functionalityBin Meng2020-06-191-1/+23
* hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng2020-06-191-1/+3
* hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2020-06-191-2/+41
* hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng2020-06-191-11/+19
* hw/riscv: sifive_gpio: Clean up the codesBin Meng2020-06-191-8/+5Star
* hw/riscv: sifive_u: Generate device tree node for OTPBin Meng2020-06-191-0/+11
* hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng2020-06-191-6/+1Star
* hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-15/+14Star
* hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-12/+12
* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-2/+23
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-2/+12
* hw/char: Initial commit of Ibex UARTAlistair Francis2020-06-191-0/+4
* riscv/opentitan: Fix the ROM sizeAlistair Francis2020-06-191-1/+2
* sifive_e: Support the revB machineAlistair Francis2020-06-191-4/+30
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-154-12/+6Star
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-153-31/+19Star
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-152-8/+6Star
* sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster2020-06-155-6/+6
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-154-17/+6Star
* qom: Tidy up a few object_initialize_child() callsMarkus Armbruster2020-06-151-1/+1
* qdev: Convert uses of qdev_create() manuallyMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster2020-06-155-10/+14
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-155-18/+14Star
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-033-0/+190
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-11/+30
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-217/+0Star
* hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng2020-06-031-10/+10
* hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng2020-06-031-12/+12
* riscv: Change the default behavior if no -bios option is specifiedBin Meng2020-06-031-27/+4Star
* riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng2020-06-031-3/+11
* hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé2020-05-181-1/+1
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-152-7/+8
* qom: Drop object_property_set_description() parameter @errpMarkus Armbruster2020-05-151-3/+2Star
* hw/riscv/spike: Allow more than one CPUsAnup Patel2020-04-291-1/+1
* hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel2020-04-291-1/+23
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-293-7/+10
* riscv: sifive_e: Support changing CPU typeCorey Wharton2020-04-291-2/+3
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-293-0/+12
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+20
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