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* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-107-529/+9Star
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-108-272/+10Star
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-105-406/+2Star
* hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-103-192/+1Star
* hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-103-170/+1Star
* hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-104-127/+2Star
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-102-0/+31
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-106-16/+28
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+14
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+39
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-102-0/+16
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-102-0/+24
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-102-0/+31
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-103-0/+319
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-103-0/+4
* hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+3
* riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor2020-09-101-1/+1
* configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini2020-09-081-1/+1
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-42/+42
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-227/+299
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-74/+158
* hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2020-08-252-0/+243
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-254-14/+16
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-255-12/+16
* hw/riscv: spike: Change the default bios to use generic platform imageBin Meng2020-08-221-2/+7
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-222-4/+4
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+22
* meson: convert hw/arch*Marc-André Lureau2020-08-212-16/+19
* trace: switch position of headers to what Meson requiresPaolo Bonzini2020-08-211-0/+1
* hw/riscv: sifive_e: Correct debug block sizeBin Meng2020-07-221-1/+1
* hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-211-0/+1
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-143-3/+3
* RISC-V: Support 64 bit start addressAtish Patra2020-07-142-2/+10
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-144-15/+72
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-144-32/+63
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-144-76/+52Star
* hw/riscv: virt: Sort the SoC memmap table entriesBin Meng2020-07-141-3/+3
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-103-12/+4Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-105-11/+11
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-103-8/+4Star
* hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis2020-07-021-1/+1
* riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke2020-07-021-1/+2
* riscv: plic: Honour source prioritiesJessica Clarke2020-07-021-5/+12
* riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster2020-07-021-9/+5Star
* riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster2020-07-021-3/+9
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+4
* hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng2020-06-191-2/+2
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-8/+31
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-192-7/+9
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+7
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