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* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-107-529/+9Star
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-108-272/+10Star
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_clint model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-105-406/+2Star
| | | | | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory. Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-103-192/+1Star
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_otp model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-103-170/+1Star
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-104-127/+2Star
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_e_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-102-0/+31
| | | | | | | | | | | SiFive FU540 SoC integrates a platform DMA controller with 4 DMA channels. This connects the exsiting SiFive PDMA model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-106-16/+28
| | | | | | | | | | | | | | At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+14
| | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+39
| | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-102-0/+16
| | | | | | | | | | | On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-102-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-102-0/+31
| | | | | | | | | | Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-103-0/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-103-0/+4
| | | | | | | | | | | | | Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+3
| | | | | | | | | | | | | RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor2020-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [ 4.999630] reboot: Power down sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000 sbi_trap_error: hart0: t6=0x0000000000000000 The kernel does a 16-bit write when powering off the machine, which was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""). Make min_access_size match reality so that the machine can shut down properly now. Cc: qemu-stable@nongnu.org Fixes: 88a07990fa ("SiFive RISC-V Test Finisher") Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini2020-09-081-1/+1
| | | | | | | | | | | | All Meson executables should specify their dependencies explicitly, either directly or indirectly via declare_dependency. Makefiles instead did not propagate dependencies correctly from static libraries, for example. Therefore, flags for dependencies need not be included in QEMU_CFLAGS. LIBS is not used at all, so drop that one as well. In a few cases the dependencies were not yet specified, so add them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-42/+42
| | | | | | | | | | | | | | | | Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-227/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a NUMA node having a set of HARTs, a memory instance, a CLINT instance, and a PLIC instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V virt machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V virt machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-74/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2020-08-252-0/+243
| | | | | | | | | | | | | | | | We add common helper routines which can be shared by RISC-V multi-socket NUMA machines. We have two types of helpers: 1. riscv_socket_xyz() - These helper assist managing multiple sockets irrespective whether QEMU NUMA is enabled/disabled 2. riscv_numa_xyz() - These helpers assist in providing necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-254-14/+16
| | | | | | | | | | | | We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-255-12/+16
| | | | | | | | | | | | We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: spike: Change the default bios to use generic platform imageBin Meng2020-08-221-2/+7
| | | | | | | | | | | | | | To keep sync with other RISC-V machines, change the default bios to use generic platform fw_dynamic.elf image. While we are here, add some comments to mention that using ELF files for the Spike machine was intentional. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1596439832-29238-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-222-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update virt and sifive_u machines to use the opensbi fw_dynamic bios image built for the generic FDT platform. Remove the out-of-date no longer used bios images. Note: 1. To test 32-bit Linux kernel on QEMU 'sifive_u' 32-bit machine, the following patch is needed: http://lists.infradead.org/pipermail/linux-riscv/2020-July/001213.html 2. To test 64-bit Linux 5.3 kernel on QEMU 'virt' or 'sifive_u' 64-bit machines, the following commit should be cherry-picked to 5.3: commit 922b0375fc93fb1a20c5617e37c389c26bbccb70 Author: Albert Ou <aou@eecs.berkeley.edu> Date: Fri Sep 27 16:14:18 2019 -0700 riscv: Fix memblock reservation for device tree blob Linux 5.4 or above already contains this commit/fix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1596439832-29238-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+22
| | | | | | | | | | | It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* meson: convert hw/arch*Marc-André Lureau2020-08-212-16/+19
| | | | | | | | Each architecture's sourceset is placed in an hw_arch dictionary, and picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* trace: switch position of headers to what Meson requiresPaolo Bonzini2020-08-211-0/+1
| | | | | | | | | | | | | | | | | Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/riscv: sifive_e: Correct debug block sizeBin Meng2020-07-221-1/+1
| | | | | | | | | | | | | | | Currently the debug region size is set to 0x100, but according to FE310-G000 and FE310-G002 manuals: FE310-G000: 0x100 - 0xFFF FE310-G002: 0x0 - 0xFFF Change the size to 0x1000 that applies to both. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-211-0/+1
| | | | | | | | | | | | | | | nd_table[] contains NIC configuration for boards to pick up. Device code has no business looking there. Several devices do it anyway. Two of them already have a suitable FIXME comment: "allwinner-a10" and "msf2-soc". Copy it to the others: "allwinner-h3", "xlnx-versal", "xlnx,zynqmp", "sparc32-ledma", "riscv.sifive.u.soc". Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200715140440.3540942-3-armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-143-3/+3
| | | | | | | | | | | At present the size of Mask ROM for sifive_u / spike / virt machines is set to 0x11000, which ends at an unusual address. This changes the size to 0xf000 so that it ends at 0x10000. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Support 64 bit start addressAtish Patra2020-07-142-2/+10
| | | | | | | | | | | | | Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-5-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-144-15/+72
| | | | | | | | | | | | | | | | | | | | | | OpenSBI is the default firmware in Qemu and has various firmware loading options. Currently, qemu loader uses fw_jump which has a compile time pre-defined address where fdt & kernel image must reside. This puts a constraint on image size of the Linux kernel depending on the fdt location and available memory. However, fw_dynamic allows the loader to specify the next stage location (i.e. Linux kernel/U-Boot) in memory and other configurable boot options available in OpenSBI. Add support for OpenSBI dynamic firmware loading support. This doesn't break existing setup and fw_jump will continue to work as it is. Any other firmware will continue to work without any issues as long as it doesn't expect anything specific from loader in "a2" register. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-4-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-144-32/+63
| | | | | | | | | | | | | | | Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-3-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-144-76/+52Star
| | | | | | | | | | | | | | | Currently, all riscv machines except sifive_u have identical reset vector code implementations with memory addresses being different for all machines. They can be easily combined into a single function in common code. Move it to common function and let all the machines use the common function. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-2-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: virt: Sort the SoC memmap table entriesBin Meng2020-07-141-3/+3
| | | | | | | | | Adjust the PCIe memory maps to follow the order. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-103-12/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... } to if (!foo(..., errp)) { ... ... return ... } where nothing else needs @err. Coccinelle script: @rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) } @rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) } @depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err Not exactly elegant, I'm afraid. The "when != lbl:" is necessary to avoid transforming if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err); even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize(). Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here. The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable(). Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-105-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The object_property_set_FOO() setters take property name and value in an unusual order: void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp) Having to pass value before name feels grating. Swap them. Same for object_property_set(), object_property_get(), and object_property_parse(). Convert callers with this Coccinelle script: @@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp) Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-103-8/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert foo(..., &err); if (err) { ... } to if (!foo(..., &err)) { ... } for qdev_realize(), qdev_realize_and_unref(), qbus_realize() and their wrappers isa_realize_and_unref(), pci_realize_and_unref(), sysbus_realize(), sysbus_realize_and_unref(), usb_realize_and_unref(). Coccinelle script: @@ identifier fun = { isa_realize_and_unref, pci_realize_and_unref, qbus_realize, qdev_realize, qdev_realize_and_unref, sysbus_realize, sysbus_realize_and_unref, usb_realize_and_unref }; expression list args, args2; typedef Error; Error *err; @@ - fun(args, &err, args2); - if (err) + if (!fun(args, &err, args2)) { ... } Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Nothing to convert there; skipped. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. A few line breaks tidied up manually. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200707160613.848843-5-armbru@redhat.com>
* hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis2020-07-021-1/+1
| | | | | | | | | | | | Commit 5d971f9e672507210e77d020d89e0e89165c8fc9 "memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"" broke most RISC-V boards as they do 64 bit accesses to the CLINT and QEMU would trigger a fault. Fix this failure by allowing 8 byte accesses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com> Message-Id: <122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
* riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke2020-07-021-1/+2
| | | | | | | | | | | | | | | | | | | | | Claiming an interrupt and changing the source priority both potentially affect whether an interrupt is pending, thus we must re-compute xEIP. Note that we don't put the sifive_plic_update inside sifive_plic_claim so that the logging of a claim (and the resulting IRQ) happens before the state update, making the causal effect clear, and that we drop the explicit call to sifive_plic_print_state when claiming since sifive_plic_update already does that automatically at the end for us. This can result in both spurious interrupt storms if you fail to complete an IRQ before enabling interrupts (and no other actions occur that result in a call to sifive_plic_update), but also more importantly lost interrupts if a disabled interrupt is pending and then becomes enabled. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: plic: Honour source prioritiesJessica Clarke2020-07-021-5/+12
| | | | | | | | | | | | The source priorities can be used to order sources with respect to other sources, not just as a way to enable/disable them based off a threshold. We must therefore always claim the highest-priority source, rather than the first source we find. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200618202343.20455-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster2020-07-021-9/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. riscv_harts_realize() is wrong that way: it passes @errp to riscv_hart_realize() in a loop. I can't tell offhand whether this can fail. Fix by checking for failure in each iteration. Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200630090351.1247703-19-armbru@redhat.com>
* riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster2020-07-021-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. sifive_u_soc_realize() is wrong that way: it passes &err to sysbus_realize() four times before checking it. Harmless, because the first three can't actually fail (I think). Fix by checking for failure right away. Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200630090351.1247703-18-armbru@redhat.com>
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is enough to simply map the SiFive FU540 DDR memory controller into the MMIO space using create_unimplemented_device(), to make the upstream U-Boot v2020.07 DDR memory initialization codes happy. Note we do not generate device tree fragment for the DDR memory controller. Since the controller data in device tree consumes a very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the U-Boot source), and it is only needed by U-Boot SPL but not any operating system, we choose not to generate the fragment here. This also means when testing with U-Boot SPL, the device tree has to come from U-Boot SPL itself, but not the one generated by QEMU on the fly. The memory has to be set to 8GiB to match the real HiFive Unleashed board when invoking QEMU (-m 8G). With this commit, QEMU can boot U-Boot SPL built for SiFive FU540 all the way up to loading U-Boot proper from MMC: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800) Trying to boot from MMC1 Unhandled exception: Load access fault EPC: 0000000008009be6 TVAL: 0000000010050014 The above exception is expected because QSPI is unsupported yet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng2020-06-191-2/+2
| | | | | | | | | | Move the flash and DRAM to the end of the SoC memmap table. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | SiFive FU540 SoC supports booting from several sources, which are controlled using the Mode Select (MSEL[3:0]) pins on the chip. Typically, the boot process runs through several stages before it begins execution of user-provided programs. The SoC supports booting from memory-mapped QSPI flash, which is how start_in_flash property is used for at present. This matches MSEL = 1 configuration (QSPI0). Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL). It's not necessary for QEMU to implement the full ZSBL ROM codes, because we know ZSBL downloads the next stage program into the L2 LIM at address 0x8000000 and executes from there. We can bypass the whole ZSBL execution and use "-bios" to load the next stage program directly if MSEL indicates a ZSBL booting flow. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-192-7/+9
| | | | | | | | | | | Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+7
| | | | | | | | | | | | | | On SiFive FU540 SoC, the value stored at physical address 0x1000 stores the MSEL pin state that is used to control the next boot location that ROM codes jump to. Add a new property msel to sifive_u machine for this. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 13:04:38 +0100