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* riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+9
* riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-172-0/+192
* riscv: sifive_u: Change UART node name in device treeBin Meng2019-09-171-1/+1
* riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
* riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-3/+4
* riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-1/+23
* riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+23
* riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-172-0/+170
* riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng2019-09-171-3/+4
* riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-171-25/+67
* riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-171-1/+4
* riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2019-09-171-1/+2
* riscv: hart: Extract hart realize to a separate routineBin Meng2019-09-171-13/+20
* riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2019-09-172-15/+9Star
* riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2019-09-171-1/+1
* riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng2019-09-171-1/+1
* riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-173-43/+42Star
* riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng2019-09-171-1/+0Star
* riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng2019-09-173-3/+0Star
* riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng2019-09-173-9/+13
* riscv: hw: Change create_fdt() to return voidBin Meng2019-09-172-14/+8Star
* riscv: hw: Remove not needed PLIC properties in device treeBin Meng2019-09-172-4/+0Star
* riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2019-09-172-21/+21
* riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-173-8/+0Star
* riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2019-09-172-2/+0Star
* riscv: sifive_test: Add reset functionalityBin Meng2019-09-171-0/+4
* riscv: Resolve full path of the given bios imageBin Meng2019-09-171-3/+3
* riscv: Add a helper routine for finding firmwareBin Meng2019-09-171-7/+15
* riscv: plic: Remove unused interrupt functionsAlistair Francis2019-09-171-12/+0Star
* riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck2019-09-171-1/+1
* riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck2019-09-171-2/+17
* riscv: sifive_u: Add support for loading initrdGuenter Roeck2019-09-171-3/+17
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-164-0/+4
* Include hw/boards.h a bit lessMarkus Armbruster2019-08-161-1/+1
* Include hw/qdev-properties.h lessMarkus Armbruster2019-08-165-0/+5
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-167-4/+3Star
* Include migration/vmstate.h lessMarkus Armbruster2019-08-161-0/+1
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-162-0/+2
* Include sysemu/reset.h a lot lessMarkus Armbruster2019-08-161-0/+1
* riscv/boot: Fixup the RISC-V firmware warningAlistair Francis2019-07-271-4/+8
* hw/riscv: Load OpenSBI as the default firmwareAlistair Francis2019-07-183-6/+66
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-055-6/+18
* hw/riscv: Extend the kernel loading supportAlistair Francis2019-06-271-4/+14
* hw/riscv: Add support for loading a firmwareAlistair Francis2019-06-273-0/+34
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-276-93/+83Star
* riscv: sifive_u: Update the plic hart config to support multicoreBin Meng2019-06-271-1/+15
* riscv: sifive_u: Do not create hard-coded phandles in DTBin Meng2019-06-271-7/+10
* riscv: virt: Add cpu-topology DT node.Atish Patra2019-06-261-2/+20
* RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt2019-06-241-7/+6Star
* riscv: virt: Correct pci "bus-range" encodingBin Meng2019-06-241-1/+1
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