summaryrefslogtreecommitdiffstats
path: root/hw
Commit message (Expand)AuthorAgeFilesLines
* util: rename qemu_open() to qemu_open_old()Daniel P. Berrangé2020-09-164-6/+6
* virtio-gpu: build modularGerd Hoffmann2020-09-151-16/+6Star
* virtio-gpu: make virtio_gpu_ops staticGerd Hoffmann2020-09-152-9/+10
* meson: remove duplicate qxl sourcesGerd Hoffmann2020-09-151-2/+0Star
* meson: fix qxl dependenciesGerd Hoffmann2020-09-151-1/+2
* hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen2020-09-141-0/+32
* hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsjHavard Skinnemoen2020-09-141-0/+20
* hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen2020-09-145-0/+643
* hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen2020-09-143-0/+91
* hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen2020-09-143-0/+470
* hw/arm: Load -bios image as a boot ROM for npcm7xxHavard Skinnemoen2020-09-141-0/+32
* hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen2020-09-142-1/+146
* hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen2020-09-143-0/+413
* hw/timer: Add NPCM7xx Timer device modelHavard Skinnemoen2020-09-143-0/+549
* hw/misc: Add NPCM7xx Clock Controller device modelHavard Skinnemoen2020-09-143-0/+271
* hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen2020-09-144-0/+279
* hw/arm: versal-virt: Correct the tx/rx GEM clocksEdgar E. Iglesias2020-09-141-1/+1
* hw/arm/mps2: New board model mps2-an500Peter Maydell2020-09-141-10/+55
* hw/arm/mps2: New board model mps2-an386Peter Maydell2020-09-141-5/+29
* hw/timer/armv7m_systick: assert that board code set system_clock_scalePeter Maydell2020-09-141-0/+8
* hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)Philippe Mathieu-Daudé2020-09-141-0/+6
* hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fieldsPhilippe Mathieu-Daudé2020-09-141-11/+5Star
* hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fieldsPhilippe Mathieu-Daudé2020-09-141-16/+5Star
* hw/misc/a9scu: Do not allow invalid CPU countPhilippe Mathieu-Daudé2020-09-141-5/+13
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-1341-87/+1300
|\
| * hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng2020-09-101-29/+29
| * hw/riscv: Drop CONFIG_SIFIVEBin Meng2020-09-101-9/+5Star
| * hw/riscv: Always build riscv_hart.cBin Meng2020-09-102-10/+1Star
| * hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-106-3/+7
| * hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-107-4/+9
| * hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-106-6/+6
| * hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-1010-6/+95
| * hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-1010-7/+15
| * hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-108-10/+13
| * hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-105-2/+6
| * hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-105-2/+6
| * hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-106-3/+9
| * hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-102-0/+31
| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-106-16/+28
| * hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+14
| * hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+39
| * hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23Bin Meng2020-09-104-3/+7
| * hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng2020-09-101-2/+3
| * hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-102-0/+16
| * hw/dma: Add SiFive platform DMA controller emulationBin Meng2020-09-103-0/+317
| * hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-102-0/+24
| * hw/sd: Add Cadence SDHCI emulationBin Meng2020-09-103-0/+198
| * hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-102-0/+31
| * hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng2020-09-103-0/+90
| * hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-103-0/+319
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-13 23:59:28 +0200