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bwlp/qemu.git
block_qcow2_cluster_info
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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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Commit message (
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Author
Age
Files
Lines
*
hw/timer/hpet: Remove unused functions hpet_ram_readb, hpet_ram_readw
Dov Murik
2020-09-16
1
-14
/
+0
*
hw/ppc/ppc4xx_pci: Replace magic value by the PCI_NUM_PINS definition
Philippe Mathieu-Daudé
2020-09-16
1
-1
/
+1
*
hw/gpio/max7310: Remove impossible check
Philippe Mathieu-Daudé
2020-09-16
1
-4
/
+1
*
virtio-gpu: build modular
Gerd Hoffmann
2020-09-15
1
-16
/
+6
*
virtio-gpu: make virtio_gpu_ops static
Gerd Hoffmann
2020-09-15
2
-9
/
+10
*
meson: remove duplicate qxl sources
Gerd Hoffmann
2020-09-15
1
-2
/
+0
*
meson: fix qxl dependencies
Gerd Hoffmann
2020-09-15
1
-1
/
+2
*
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
Havard Skinnemoen
2020-09-14
1
-0
/
+32
*
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
Havard Skinnemoen
2020-09-14
1
-0
/
+20
*
hw/ssi: NPCM7xx Flash Interface Unit device model
Havard Skinnemoen
2020-09-14
5
-0
/
+643
*
hw/mem: Stubbed out NPCM7xx Memory Controller model
Havard Skinnemoen
2020-09-14
3
-0
/
+91
*
hw/nvram: NPCM7xx OTP device model
Havard Skinnemoen
2020-09-14
3
-0
/
+470
*
hw/arm: Load -bios image as a boot ROM for npcm7xx
Havard Skinnemoen
2020-09-14
1
-0
/
+32
*
hw/arm: Add two NPCM7xx-based machines
Havard Skinnemoen
2020-09-14
2
-1
/
+146
*
hw/arm: Add NPCM730 and NPCM750 SoC models
Havard Skinnemoen
2020-09-14
3
-0
/
+413
*
hw/timer: Add NPCM7xx Timer device model
Havard Skinnemoen
2020-09-14
3
-0
/
+549
*
hw/misc: Add NPCM7xx Clock Controller device model
Havard Skinnemoen
2020-09-14
3
-0
/
+271
*
hw/misc: Add NPCM7xx System Global Control Registers device model
Havard Skinnemoen
2020-09-14
4
-0
/
+279
*
hw/arm: versal-virt: Correct the tx/rx GEM clocks
Edgar E. Iglesias
2020-09-14
1
-1
/
+1
*
hw/arm/mps2: New board model mps2-an500
Peter Maydell
2020-09-14
1
-10
/
+55
*
hw/arm/mps2: New board model mps2-an386
Peter Maydell
2020-09-14
1
-5
/
+29
*
hw/timer/armv7m_systick: assert that board code set system_clock_scale
Peter Maydell
2020-09-14
1
-0
/
+8
*
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
Philippe Mathieu-Daudé
2020-09-14
1
-0
/
+6
*
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
Philippe Mathieu-Daudé
2020-09-14
1
-11
/
+5
*
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
Philippe Mathieu-Daudé
2020-09-14
1
-16
/
+5
*
hw/misc/a9scu: Do not allow invalid CPU count
Philippe Mathieu-Daudé
2020-09-14
1
-5
/
+13
*
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...
Peter Maydell
2020-09-13
41
-87
/
+1300
|
\
|
*
hw/riscv: Sort the Kconfig options in alphabetical order
Bin Meng
2020-09-10
1
-29
/
+29
|
*
hw/riscv: Drop CONFIG_SIFIVE
Bin Meng
2020-09-10
1
-9
/
+5
|
*
hw/riscv: Always build riscv_hart.c
Bin Meng
2020-09-10
2
-10
/
+1
|
*
hw/riscv: Move sifive_test model to hw/misc
Bin Meng
2020-09-10
6
-3
/
+7
|
*
hw/riscv: Move sifive_uart model to hw/char
Bin Meng
2020-09-10
7
-4
/
+9
|
*
hw/riscv: Move riscv_htif model to hw/char
Bin Meng
2020-09-10
6
-6
/
+6
|
*
hw/riscv: Move sifive_plic model to hw/intc
Bin Meng
2020-09-10
10
-6
/
+95
|
*
hw/riscv: Move sifive_clint model to hw/intc
Bin Meng
2020-09-10
10
-7
/
+15
|
*
hw/riscv: Move sifive_gpio model to hw/gpio
Bin Meng
2020-09-10
8
-10
/
+13
|
*
hw/riscv: Move sifive_u_otp model to hw/misc
Bin Meng
2020-09-10
5
-2
/
+6
|
*
hw/riscv: Move sifive_u_prci model to hw/misc
Bin Meng
2020-09-10
5
-2
/
+6
|
*
hw/riscv: Move sifive_e_prci model to hw/misc
Bin Meng
2020-09-10
6
-3
/
+9
|
*
hw/riscv: sifive_u: Connect a DMA controller
Bin Meng
2020-09-10
2
-0
/
+31
|
*
hw/riscv: clint: Avoid using hard-coded timebase frequency
Bin Meng
2020-09-10
6
-16
/
+28
|
*
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Bin Meng
2020-09-10
1
-0
/
+14
|
*
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Bin Meng
2020-09-10
1
-0
/
+39
|
*
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
Bin Meng
2020-09-10
4
-3
/
+7
|
*
hw/net: cadence_gem: Add a new 'phy-addr' property
Bin Meng
2020-09-10
1
-2
/
+3
|
*
hw/riscv: microchip_pfsoc: Connect a DMA controller
Bin Meng
2020-09-10
2
-0
/
+16
|
*
hw/dma: Add SiFive platform DMA controller emulation
Bin Meng
2020-09-10
3
-0
/
+317
|
*
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
Bin Meng
2020-09-10
2
-0
/
+24
|
*
hw/sd: Add Cadence SDHCI emulation
Bin Meng
2020-09-10
3
-0
/
+198
|
*
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Bin Meng
2020-09-10
2
-0
/
+31
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