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* ipmi: Add support to customize OEM functionsCédric Le Goater2019-12-171-44/+6Star
* ppc/xive: Check V bit in TM_PULL_POOL_CTXCédric Le Goater2019-12-171-0/+5
* ppc/xive: Introduce OS CAM line helpersCédric Le Goater2019-12-171-3/+38
* ppc/pnv: Quiesce some XIVE errorsCédric Le Goater2019-12-171-1/+5
* xive/kvm: Trigger interrupts from userspaceGreg Kurz2019-12-171-14/+2Star
* ppc/pnv: Remove pnv_xive_vst_size() routineCédric Le Goater2019-12-171-69/+43Star
* ppc/xive: Record the IPB in the associated NVTCédric Le Goater2019-12-171-2/+9
* ppc/pnv: Add a LPC "ranges" propertyCédric Le Goater2019-12-171-1/+13
* spapr: Abort if XICS interrupt controller cannot be initializedGreg Kurz2019-12-171-11/+2Star
* xics: Link ICP_PROP_CPU property to ICPState::cs pointerGreg Kurz2019-12-171-17/+4Star
* xics: Link ICP_PROP_XICS property to ICPState::xics pointerGreg Kurz2019-12-171-13/+9Star
* xics: Link ICS_PROP_XICS property to ICSState::xics pointerGreg Kurz2019-12-173-19/+6Star
* ppc/pnv: Link "chip" property to PnvXive::chip pointerGreg Kurz2019-12-172-12/+5Star
* ppc/pnv: Link "chip" property to PnvCore::chip pointerGreg Kurz2019-12-172-10/+4Star
* ppc/pnv: Link "chip" property to PnvHomer::chip pointerGreg Kurz2019-12-172-14/+14
* ppc/pnv: Link "psi" property to PnvOCC::psi pointerGreg Kurz2019-12-172-15/+13Star
* ppc/pnv: Link "psi" property to PnvLpc::psi pointerGreg Kurz2019-12-172-15/+12Star
* xive: Link "xive" property to XiveEndSource::xrtr pointerGreg Kurz2019-12-173-14/+7Star
* xive: Link "xive" property to XiveSource::xive pointerGreg Kurz2019-12-174-16/+8Star
* xive: Link "cpu" property to XiveTCTX::cs pointerGreg Kurz2019-12-171-13/+9Star
* ppc/pnv: Drop "chip" link from POWER9 PSI objectGreg Kurz2019-12-171-2/+0Star
* ppc/pnv: Add a "/qemu" device tree nodeCédric Le Goater2019-12-171-0/+3
* ppc/pnv: Add a PNOR modelCédric Le Goater2019-12-173-1/+152
* Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' ...Peter Maydell2019-12-168-242/+278
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| * hw/mips: Deprecate the r4k machinePhilippe Mathieu-Daudé2019-12-161-0/+1
| * mips: fulong 2e: Renovate coding styleFilip Bozuta2019-12-162-38/+45
| * mips: r4000: Renovate coding styleFilip Bozuta2019-12-161-21/+34
| * mips: mipssim: Renovate coding styleFilip Bozuta2019-12-161-19/+23
| * mips: malta: Renovate coding styleFilip Bozuta2019-12-161-85/+87
| * mips: jazz: Renovate coding styleFilip Bozuta2019-12-163-79/+88
* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191216-...Peter Maydell2019-12-1616-313/+832
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| * | hw/arm/virt: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé2019-12-161-55/+54Star
| * | hw/arm/acpi: enable SHPC native hot plugHeyi Guo2019-12-161-1/+6
| * | hw/arm/acpi: simplify AML bit and/or statementHeyi Guo2019-12-161-8/+8
| * | hw/arm/sbsa-ref: Simplify by moving the gic in the machine statePhilippe Mathieu-Daudé2019-12-161-44/+42Star
| * | aspeed: Change the "nic" property definitionCédric Le Goater2019-12-162-13/+11Star
| * | aspeed: Change the "scu" property definitionCédric Le Goater2019-12-164-25/+25
| * | gpio: fix memory leak in aspeed_gpio_init()PanNengyuan2019-12-161-0/+1
| * | aspeed: Add support for the tacoma-bmc boardCédric Le Goater2019-12-161-0/+28
| * | aspeed: Remove AspeedBoardConfig array and use AspeedMachineClassCédric Le Goater2019-12-161-104/+127
| * | aspeed/smc: Add AST2600 timings registersCédric Le Goater2019-12-161-3/+14
| * | aspeed/smc: Do not map disabled segment on the AST2600Cédric Le Goater2019-12-161-5/+11
| * | aspeed/smc: Restore default AHB window mapping at resetCédric Le Goater2019-12-161-11/+21
| * | watchdog/aspeed: Fix AST2600 frequency behaviourJoel Stanley2019-12-161-4/+17
| * | watchdog/aspeed: Improve watchdog timeout messageJoel Stanley2019-12-161-1/+2
| * | aspeed/scu: Fix W1C behaviorJoel Stanley2019-12-161-5/+14
| * | aspeed/sdmc: Make ast2600 default 1GJoel Stanley2019-12-161-3/+3
| * | aspeed/i2c: Add trace eventsCédric Le Goater2019-12-162-13/+89
| * | aspeed/i2c: Add support for DMA transfersCédric Le Goater2019-12-163-3/+133
| * | aspeed: Add a DRAM memory region at the SoC levelCédric Le Goater2019-12-162-4/+12
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