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* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+3
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+7
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+11
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+4
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+20
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+88
* hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-19/+19
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-2/+7
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-2/+9
* hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2020-08-251-0/+113
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-5/+7
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-3/+4
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+4
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-142-1/+62
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+3
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-0/+2
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+1
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-0/+6
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+1
* hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2020-06-191-0/+19
* hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng2020-06-191-0/+3
* hw/riscv: sifive_gpio: Clean up the codesBin Meng2020-06-191-3/+4
* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-0/+13
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-0/+3
* sifive_e: Support the revB machineAlistair Francis2020-06-191-0/+1
* riscv: Fix type of SiFive[EU]SocState, member parent_objMarkus Armbruster2020-06-152-2/+2
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-031-0/+68
* riscv/boot: Add a missing header includeAlistair Francis2020-06-031-0/+1
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-0/+4
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-4/+2Star
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-2/+4
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+1
* riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis2020-04-291-0/+2
* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+2
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+2
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-1/+2
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-281-0/+3
* riscv/virt: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-0/+2
* riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+1
* riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+1
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-283-9/+0Star
* riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-2/+1Star
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-1/+2
* riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+3
* riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-171-0/+80
* riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
* riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-0/+10
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