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* target-mips: microMIPS32 R6 Major instructionsYongbok Kim2015-06-261-17/+45
| | | | | | | | Add new microMIPS32 Release 6 Major opcode instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim2015-06-261-6/+21
| | | | | | | | | Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim2015-06-261-32/+199
| | | | | | | | | Add new microMIPS32 Release 6 POOL32F instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim2015-06-261-10/+72
| | | | | | | | | Add new microMIPS32 Release 6 pool32a/pool32axf instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: microMIPS32 R6 branches and jumpsYongbok Kim2015-06-261-40/+202
| | | | | | | | | Add new microMIPS32 Release 6 branch and jump instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add microMIPS32 R6 opcode enumYongbok Kim2015-06-261-16/+103
| | | | | | | | | Add microMIPS32 Release 6 opcode enum. Remove RI checking for pre-R6 reserved opcode. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim2015-06-261-0/+68
| | | | | | | | | | Signal a Reserved Instruction exception for removed instruction encoding in microMIPS Release 6. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim2015-06-261-33/+45
| | | | | | | | | | | | | | | 64-bit paired-single (PS) floating point data type is optional in the pre-Release 6. It has to raise RI exception when PS type is not implemented. (FIR.PS = 0) (The PS data type is removed in the Release 6.) Loongson-2E and Loongson-2F don't have any implementation field in FCSR0(FIR) but do support PS data format, therefore for these cores RI will not be signalled regardless of PS bit. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: rearrange gen_compute_compact_branchYongbok Kim2015-06-261-236/+236
| | | | | | | | | The function will be also used for microMIPS Release 6. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim2015-06-261-67/+99
| | | | | | | | | | | Refactor those instructions in order to reuse them for microMIPS32 Release 6. Rearrange gen_move_low32(). Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: remove an unused argumentYongbok Kim2015-06-261-3/+2Star
| | | | | | | | | Remove an unused argument from decode_micromips32_opc() Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add microMIPS TLBINV, TLBINVFYongbok Kim2015-06-261-0/+8
| | | | | | | | | Add microMIPS TLBINV, TLBINVF Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: fix {RD, WR}PGPR in microMIPSYongbok Kim2015-06-261-2/+2
| | | | | | | | | rt, rs were swapped Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae2015-06-261-20/+55
| | | | | | | | | | | | | Add UHI semihosting support for MIPS. QEMU run with "-semihosting" option will alter the behaviour of SDBBP 1 instruction -- UHI operation will be called instead of generating a debug exception. Also tweak Malta's pseudo-bootloader. On CPU reset the $4 register is set to -1 if semihosting arguments are passed to indicate that the UHI operations should be used to obtain input arguments. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: remove identical code in different branchLeon Alrae2015-06-261-21/+4Star
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae2015-06-121-0/+226
| | | | | | | | | | | | | | Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-121-21/+42
| | | | | | | | | | | Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae2015-06-121-6/+6
| | | | | | | CP0.EntryLo bits 31:30 have to be cleared. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-5/+15
| | | | | | | | | | | ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Misaligned memory accesses for MSAYongbok Kim2015-06-111-10/+17
| | | | | | | | | | | | | | | | | | MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove unused do_* functions] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Misaligned memory accesses for R6Yongbok Kim2015-06-111-12/+27
| | | | | | | | | | | Release 6 requires misaligned memory access support for all ordinary memory access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory accesses such as atomics (for example, LL/SC). Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-111-150/+158
| | | | | | | | | | | | | | | | | | This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: move group of functions above gen_load_fpr32()Leon Alrae2015-06-111-60/+58Star
| | | | | | | Move the "Tests" group of functions so that gen_load_fpr32() and gen_store_fpr32() can use generate_exception(). Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: save cpu state before calling MSA load and store helpersLeon Alrae2015-03-181-0/+2
| | | | | | | | PC needs to be saved if an exception can be generated by an helper. This fixes a problem related to resuming the execution at unexpected address after an exception (caused by MSA load/store instruction) has been serviced. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: fix hflags modified in delay / forbidden slotLeon Alrae2015-03-181-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | All instructions which may change hflags terminate tb. However, this doesn't work if such an instruction is placed in delay or forbidden slot. gen_branch() clears MIPS_HFLAG_BMASK in ctx->hflags and then generates code to overwrite hflags with ctx->hflags, consequently we loose any execution-time hflags modifications. For example, in the following scenario hflag related to Status.CU1 will not be updated: /* Set Status.CU1 in delay slot */ mfc0 $24, $12, 0 lui $25, 0x2000 or $25, $25, $24 b check_Status_CU1 mtc0 $25, $12, 0 With this change we clear MIPS_HFLAG_BMASK in execution-time hflags if instruction in delay or forbidden slot wants to terminate tb for some reason (i.e. ctx->bstate != BS_NONE). Also, die early and loudly if "unknown branch" is encountered as this should never happen. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae2015-03-181-0/+1
| | | | | | | | | CP0.BadVAddr is supposed to capture the most recent virtual address that caused the exception. Currently this does not work correctly for unaligned instruction fetch as translation is not stopped and CP0.BadVAddr is updated with subsequent addresses. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae2015-02-131-1/+1
| | | | | | | | | Using rs = -1 in gen_logic_imm() for microMIPS LUI instruction is dangerous and may bite us when implementing microMIPS R6 because in R6 AUI and LUI are distinguished by rs value. Therefore use 0 for safety. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae2015-02-131-2/+2
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
* target-mips: fix detection of the end of the page during translationLeon Alrae2015-02-131-1/+4
| | | | | | | | | | | The test is supposed to terminate TB if the end of the page is reached. However, with current implementation it may never succeed for microMIPS or mips16. Reported-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-5/+3Star
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+1
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: Clean up switch fall through after commit fecd264Markus Armbruster2015-02-101-0/+4
| | | | | | | | | | | Commit fecd264 added a number of fall-throughs, but neglected to properly document them as intentional. Commit d922445 cleaned that up for many, but not all cases. Take care of the remaining ones. Spotted by Coverity. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-10/+14
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-mips: convert single case switch into if statementLeon Alrae2014-12-161-3/+1Star
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki2014-12-161-1/+1
| | | | | | | | Set DisasContext's ulri member to 0 or 1 as with other bool members. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-0/+2
| | | | | | | | | | | | | | | | Add missing calls to synchronise the SoftFloat status with the CP1.FSCR: + for the rounding and flush-to-zero modes upon processor reset, + for the flush-to-zero mode on FSCR updates through the GDB stub. Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE macro. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-161-5/+14
| | | | | | | | | | | | | | | | | Make sure the address space is unconditionally wrapped on 32-bit processors, that is ones that do not implement at least the MIPS III ISA. Also make MIPS16 SAVE and RESTORE instructions use address calculation rather than plain arithmetic operations for stack pointer manipulation so that their semantics for stack accesses follows the architecture specification. That in particular applies to user software run on 64-bit processors with the CP0.Status.UX bit clear where the address space is wrapped to 32 bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-161-9/+98
| | | | | | | | | | | Tighten ISA level checks down to MIPS II that many of our instructions are missing. Also make sure any 64-bit instruction enables are only applied to 64-bit processors, that is ones that implement at least the MIPS III ISA. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-161-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This bit is mandatory for any processor that implements the microMIPS instruction set. This bit is r/w for processors that implement both the standard MIPS and the microMIPS instruction set. This bit is r/o and hardwired to 1 if only the microMIPS instruction set is implemented. There is no other bit ever writable in CP0.Config3 so defining a corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I think an overkill. Therefore make the ability to write the bit rely on the presence of ASE_MICROMIPS set in the instruction flags. The read-only case of the microMIPS instruction set being implemented only can be added when we add support for such a configuration. We do not currently have such support, we have no instruction flag that would control the presence of the standard MIPS instruction set nor any associated code in instruction decoding. This change is needed to boot a microMIPS Linux kernel successfully, otherwise it hangs early on as interrupts are enabled and then the exception handler invoked loops as its first instruction is interpreted in the wrong execution mode and triggers another exception right away. And then over and over again. We already check the current setting of the CP0.Config3.ISAOnExc in `set_hflags_for_handler' to set the ISA bit correctly on the exception handler entry so it is the ability to set it that is missing only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki2014-12-161-0/+4
| | | | | | | | | Include CP0.Config2 through CP0.Config5 registers in the register dump produced with the `info registers' monitor command. Align vertically with the registers already output. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki2014-12-161-3/+3
| | | | | | | | | | | | | | | | | | | | | Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by using register addition operations. This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying `rs' to `rd' verbatim. This is not the case with OPC_ADDIU where a sign-extension from bit #31 is made, unless in the uninteresting case of `rs' being 0, losing the upper 32 bits of the value copied for any proper 64-bit values. This also serves as an optimization as one op is produced in generated code rather than two (again, unless `rs' is 0, where it doesn't change anything). Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki2014-12-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | Correct MIPS16/microMIPS branch size calculation in PC adjustment needed: - to set the value of CP0.ErrorEPC at the entry to the reset exception, - for the purpose of branch reexecution in the context of device I/O. Follow the approach taken in `exception_resume_pc' for ordinary, Debug and NMI exceptions. MIPS16 and microMIPS branches can be 2 or 4 bytes in size and that has to be reflected in calculation. Original MIPS ISA branches, which is where this code originates from, are always 4 bytes long, just as all original MIPS ISA instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki2014-12-161-5/+8
| | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki2014-12-161-1/+1
| | | | | Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: fix multiple TCG registers covering same dataYongbok Kim2014-11-071-5/+3Star
| | | | | | | | | Avoid to allocate different TCG registers for the FPU registers that are mapped on the MSA vectore registers. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki2014-11-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the way PC is updated when single-stepping instructions, by keeping the old PC only for the BS_EXCP (exception condition) state. Some MTC0 (and possibly other) instructions switch to the BS_STOP state to terminate the current translation block, so that the state transition of the simulated CPU resulting from the CP0 operation takes effect with the following instruction. This happens with `mtc0 <reg>,c0_config' for example, typically used to set KSEG0 cacheability. While single-stepping this has a side-effect of not advancing the PC past the instruction just executed; subsequent single-step traps will stop at the same instruction repeatedly. Example: (gdb) stepi 0x80004d24 in _start () 5: x/i $pc => 0x80004d24 <_start+364>: mfc0 t1,c0_config (gdb) 0x80004d28 in _start () 5: x/i $pc => 0x80004d28 <_start+368>: li at,-8 (gdb) 0x80004d2c in _start () 5: x/i $pc => 0x80004d2c <_start+372>: and t1,t1,at (gdb) 0x80004d30 in _start () 5: x/i $pc => 0x80004d30 <_start+376>: ori t1,t1,0x3 (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) -- oops! Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 19:28:13 +0100