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* target-mips: microMIPS32 R6 Major instructionsYongbok Kim2015-06-261-17/+45
* target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim2015-06-261-6/+21
* target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim2015-06-261-32/+199
* target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim2015-06-261-10/+72
* target-mips: microMIPS32 R6 branches and jumpsYongbok Kim2015-06-261-40/+202
* target-mips: add microMIPS32 R6 opcode enumYongbok Kim2015-06-261-16/+103
* target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim2015-06-261-0/+68
* target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim2015-06-261-33/+45
* target-mips: rearrange gen_compute_compact_branchYongbok Kim2015-06-261-236/+236
* target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim2015-06-261-67/+99
* target-mips: remove an unused argumentYongbok Kim2015-06-261-3/+2Star
* target-mips: add microMIPS TLBINV, TLBINVFYongbok Kim2015-06-261-0/+8
* target-mips: fix {RD, WR}PGPR in microMIPSYongbok Kim2015-06-261-2/+2
* target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae2015-06-261-20/+55
* target-mips: remove identical code in different branchLeon Alrae2015-06-261-21/+4Star
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae2015-06-121-0/+226
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-1/+2
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-121-21/+42
* target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae2015-06-121-6/+6
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-5/+15
* target-mips: Misaligned memory accesses for MSAYongbok Kim2015-06-111-10/+17
* target-mips: Misaligned memory accesses for R6Yongbok Kim2015-06-111-12/+27
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-111-150/+158
* target-mips: move group of functions above gen_load_fpr32()Leon Alrae2015-06-111-60/+58Star
* target-mips: save cpu state before calling MSA load and store helpersLeon Alrae2015-03-181-0/+2
* target-mips: fix hflags modified in delay / forbidden slotLeon Alrae2015-03-181-4/+15
* target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae2015-03-181-0/+1
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-47/+47
* target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae2015-02-131-1/+1
* target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae2015-02-131-2/+2
* target-mips: fix detection of the end of the page during translationLeon Alrae2015-02-131-1/+4
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-5/+3Star
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+1
* target-mips: Clean up switch fall through after commit fecd264Markus Armbruster2015-02-101-0/+4
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-10/+14
* target-mips: convert single case switch into if statementLeon Alrae2014-12-161-3/+1Star
* target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki2014-12-161-1/+1
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-0/+2
* target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-161-5/+14
* target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-161-9/+98
* target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-161-2/+6
* target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki2014-12-161-0/+4
* target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki2014-12-161-3/+3
* target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki2014-12-161-1/+2
* target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki2014-12-161-5/+8
* target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki2014-12-161-1/+1
* target-mips: fix multiple TCG registers covering same dataYongbok Kim2014-11-071-5/+3Star
* mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki2014-11-071-1/+1
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