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* Fix array subscript above array bounds errorblueswir12008-09-141-1/+1
* Fix mulscc with high bits set in either src1 or src2blueswir12008-09-131-2/+3
* Write zeros to high bits of y, based on patch by Vince Weaverblueswir12008-09-111-2/+4
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-105-64/+39Star
* Partially convert float128 conversion ops to TCGblueswir12008-09-103-20/+19Star
* Convert basic 64 bit VIS ops to TCGblueswir12008-09-104-102/+65Star
* Convert basic 32 bit VIS ops to TCGblueswir12008-09-103-164/+48Star
* Convert basic float32 ops to TCGblueswir12008-09-103-190/+329
* Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir12008-09-095-31/+43
* Fix a typo in fpsub32blueswir12008-09-061-1/+1
* Convert most env fields to TCG registersblueswir12008-09-061-95/+91Star
* Silence gcc warning about constant overflowblueswir12008-09-062-3/+11
* Implement no-fault loadsblueswir12008-09-031-8/+36
* Fix sign extension problems with smul and umul (Vince Weaver)blueswir12008-09-021-4/+4
* Fix y register loads and storesblueswir12008-09-011-18/+16Star
* Remove memcpy32() prototype leftover from r5109blueswir12008-08-301-1/+0Star
* Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir12008-08-292-30/+28Star
* Fix Sparc64 boot on i386 host:blueswir12008-08-295-273/+280
* Fix udiv and sdiv on Sparc64 (Vince Weaver)blueswir12008-08-251-2/+2
* Fix wrwim masking (Luis Pureza)blueswir12008-08-211-0/+3
* Use initial CPU definition structure for some CPU fields instead of copyingblueswir12008-08-214-87/+83Star
* Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir12008-08-171-5/+8
* Fix faligndata (Vince Weaver)blueswir12008-08-061-1/+4
* Fix I/D MMU tag readsblueswir12008-08-061-54/+4Star
* Fix Sparc64 shiftsblueswir12008-08-061-5/+3Star
* Fix offset handling for ASI loads and stores (Vince Weaver)blueswir12008-08-061-3/+1Star
* Handle wrapped registers correctly when savingblueswir12008-08-011-1/+11
* Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir12008-07-291-4/+4
* Make MAXTL dynamic, bounds check tl when indexingblueswir12008-07-254-51/+56
* Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir12008-07-242-4/+110
* Add T1 and T2 CPUs, add a Sun4v machineblueswir12008-07-223-1/+26
* Use MMU globals for some MMU trapsblueswir12008-07-212-4/+19
* Fix reset vectorblueswir12008-07-211-1/+1
* Print default and available CPU features separatelyblueswir12008-07-201-4/+7
* Make UA200x features selectable, add MMU typesblueswir12008-07-204-23/+48
* Remove unused variableblueswir12008-07-191-2/+0Star
* Implement nucleus quad lddablueswir12008-07-193-20/+70
* Update TLB miss addressesblueswir12008-07-191-0/+2
* Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths2008-07-181-7/+6Star
* wrhpr hstick_cmpr is a store, not a loadblueswir12008-07-181-3/+2Star
* Fix saving and loading of trap stateblueswir12008-07-172-12/+12
* Support for address maskingblueswir12008-07-172-31/+55
* Fix MMU registers, add more E-cache ASIsblueswir12008-07-161-10/+64
* Fix MMU miss trapsblueswir12008-07-162-4/+4
* Flushw can generate exceptions, so save PC & NPCblueswir12008-07-161-0/+1
* Really fix casblueswir12008-07-151-6/+5Star
* Implement some Ultrasparc cache ASIs used by SILOblueswir12008-07-081-0/+20
* Move interrupt_request and user_mode_only to common cpu state.pbrook2008-07-011-2/+0Star
* Move CPU save/load registration to common code.pbrook2008-06-301-0/+2
* Add instruction counter.pbrook2008-06-292-1/+24
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