summaryrefslogtreecommitdiffstats
path: root/target-tilegx
Commit message (Expand)AuthorAgeFilesLines
* target-tilegx: Implement prefetch instructions in pipe y2Chen Gang2015-10-221-8/+14
* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+7
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell2015-10-082-45/+14Star
|\
| * tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-37/+4Star
| * tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
| * tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
| * target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0Star
| * target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-1/+2
| * target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+2Star
| * tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* | target-tilegx: Support iret instruction and related special registersChen Gang2015-10-074-1/+38
* | target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEM...Chen Gang2015-10-071-17/+24
* | target-tilegx: Implement v2mults instructionChen Gang2015-10-073-0/+20
* | target-tilegx: Implement v?int_* instructions.Chen Gang2015-10-073-0/+67
* | target-tilegx: Implement v2sh* instructionsChen Gang2015-10-071-1/+17
* | target-tilegx: Handle nofault prefetch instructionsRichard Henderson2015-10-071-14/+26
* | target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang2015-10-071-1/+1
* | target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGVRichard Henderson2015-10-072-3/+7
* | target-tilegx: Decode ill pseudo-instructionsChen Gang2015-10-072-15/+71
* | target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang2015-10-071-1/+7
* | target-tilegx: Implement complex multiply instructionsRichard Henderson2015-10-073-1/+73
* | target-tilegx: Implement table index instructionsRichard Henderson2015-10-071-0/+15
* | target-tilegx: Implement crc instructionsRichard Henderson2015-10-073-1/+28
* | target-tilegx: Implement v1multu instructionChen Gang2015-10-073-0/+18
* | target-tilegx: Implement v*add and v*sub instructionsChen Gang2015-10-071-21/+116
* | target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang2015-10-073-0/+73
* | target-tilegx: Tidy simd_helper.cRichard Henderson2015-10-071-4/+7
|/
* target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson2015-09-154-2/+76
* target-tilegx: Handle v1shli, v1shruiRichard Henderson2015-09-151-0/+14
* target-tilegx: Handle v4int_l/hRichard Henderson2015-09-151-0/+8
* target-tilegx: Handle atomic instructionsRichard Henderson2015-09-152-2/+82
* target-tilegx: Handle mtspr, mfsprRichard Henderson2015-09-151-3/+73
* target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson2015-09-151-0/+51
* target-tilegx: Handle mask instructionsRichard Henderson2015-09-151-2/+9
* target-tilegx: Handle scalar multiply instructionsRichard Henderson2015-09-151-0/+112
* target-tilegx: Handle conditional move instructionsRichard Henderson2015-09-151-1/+8
* target-tilegx: Handle shift instructionsRichard Henderson2015-09-151-2/+54
* target-tilegx: Handle bitfield instructionsRichard Henderson2015-09-151-0/+74
* target-tilegx: Implement system and memory management instructionsRichard Henderson2015-09-151-23/+54
* target-tilegx: Handle comparison instructionsRichard Henderson2015-09-151-6/+33
* target-tilegx: Handle conditional branch instructionsRichard Henderson2015-09-151-13/+38
* target-tilegx: Handle unconditional jump instructionsRichard Henderson2015-09-151-17/+41
* target-tilegx: Handle post-increment load and store instructionsRichard Henderson2015-09-151-8/+86
* target-tilegx: Handle basic load and store instructionsRichard Henderson2015-09-151-15/+115
* target-tilegx: Handle most bit manipulation instructionsRichard Henderson2015-09-153-1/+79
* target-tilegx: Handle arithmetic instructionsRichard Henderson2015-09-151-6/+90
* target-tilegx: Handle simple logical operationsRichard Henderson2015-09-151-3/+96
* target-tilegx: Add TILE-Gx building filesChen Gang2015-09-151-0/+1
* target-tilegx: Generate SEGV properlyRichard Henderson2015-09-152-1/+6
* target-tilegx: Framework for decoding bundlesRichard Henderson2015-09-151-0/+1145
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 19:28:59 +0100