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path: root/target-tricore/translate.c
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* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* Fix some typos found by codespellStefan Weil2016-05-181-1/+1
* tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2016-05-131-5/+15
* target-tricore: Add ftoi and itof instructionsBastian Koppelmann2016-03-231-0/+6
* target-tricore: Add cmp.f instructionBastian Koppelmann2016-03-231-0/+3
* target-tricore: Add div.f instructionBastian Koppelmann2016-03-231-0/+3
* target-tricore: Add mul.f instructionBastian Koppelmann2016-03-231-0/+3
* target-tricore: add add.f/sub.f instructionsBastian Koppelmann2016-03-231-0/+6
* target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divideBastian Koppelmann2016-03-231-2/+8
* target-tricore: Add FPU infrastructureBastian Koppelmann2016-03-231-0/+1
* target-tricore: add missing break in insn decode switch stmtBastian Koppelmann2016-03-231-0/+2
* tcg: Add type for vCPU pointersLluís Vilanova2016-03-011-1/+1
* target-tricore: add opd trap generationBastian Koppelmann2016-02-251-8/+277
* target-tricore: add illegal opcode trap generationBastian Koppelmann2016-02-251-19/+156
* target-tricore: Add trap handling & SOVF/OVF trapsBastian Koppelmann2016-02-251-2/+21
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-091-11/+11
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-031-0/+1
* tricore: Clean up includesPeter Maydell2016-01-291-0/+1
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-26/+5Star
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-7/+13
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+1Star
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-0/+2
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-10/+10
* tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson2015-08-241-6/+6
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann2015-05-301-1/+1
* target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann2015-05-301-11/+0Star
* target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann2015-05-301-1/+1
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+21
* target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+19
* target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+26
* target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2015-05-221-0/+10
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+5
* target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+39
* target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+35
* target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann2015-05-221-2/+9
* target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann2015-05-111-2/+2
* target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
* Fix typos in commentsViswesh2015-03-191-11/+11
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-161-0/+76
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann2015-03-161-0/+327
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann2015-03-161-0/+440
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann2015-03-161-0/+357
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