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path: root/target-tricore/translate.c
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* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-26/+5Star
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-7/+13
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+1Star
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-0/+2
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-10/+10
* tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson2015-08-241-6/+6
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann2015-05-301-1/+1
* target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann2015-05-301-11/+0Star
* target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann2015-05-301-1/+1
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+21
* target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+19
* target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2015-05-221-0/+26
* target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2015-05-221-0/+10
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+5
* target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+39
* target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2015-05-221-0/+35
* target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann2015-05-221-2/+9
* target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann2015-05-111-2/+2
* target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
* Fix typos in commentsViswesh2015-03-191-11/+11
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-161-0/+76
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann2015-03-161-0/+327
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann2015-03-161-0/+440
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann2015-03-161-0/+357
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+2Star
* target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann2015-03-031-0/+332
* target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann2015-03-031-0/+427
* target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann2015-03-031-0/+421
* target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann2015-03-031-14/+135
* target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann2015-03-031-2/+2
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-3/+1Star
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+0Star
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-271-0/+150
* target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann2015-01-271-0/+70
* target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann2015-01-271-0/+37
* target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann2015-01-271-0/+182
* target-tricore: Fix bugs found by coverityBastian Koppelmann2015-01-261-1/+2
* target-tricore: Several translator and cpu model fixesBastian Koppelmann2015-01-261-3/+3
* target-tricore: Fix new typosStefan Weil2015-01-151-1/+1
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-01-091-1/+1
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| * gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann2014-12-211-0/+197
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