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* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+6
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-26/+5Star
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-7/+13
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+1Star
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-0/+2
* tricore: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0Star
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-112-2/+2
* maint: remove unused include for signal.hDaniel P. Berrange2015-09-111-1/+0Star
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-10/+10
* tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson2015-08-241-6/+6
* cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite2015-07-091-1/+1
* cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite2015-07-091-1/+1
* cpu: Add Error argument to cpu_exec_init()Bharata B Rao2015-07-091-1/+1
* target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini2015-06-291-2/+2
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann2015-05-301-1/+1
* target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann2015-05-301-11/+0Star
* target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann2015-05-301-1/+1
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-224-0/+74
* target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+21
* target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+29
* target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2015-05-222-0/+11
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-224-0/+19
* target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+44
* target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+40
* target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann2015-05-221-2/+9
* target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann2015-05-222-3/+8
* target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann2015-05-221-0/+8
* target-tricore: fix rfe not restoring the PCBastian Koppelmann2015-05-111-0/+1
* target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann2015-05-111-2/+2
* target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann2015-05-111-1/+1
* tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite2015-04-301-5/+0Star
* target-tricore: Fix check which was always falseStefan Weil2015-04-041-1/+1
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
* target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann2015-03-241-30/+10Star
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
* target-tricore: Fix two helper functions (clang warnings)Stefan Weil2015-03-241-6/+6
* Fix typos in commentsViswesh2015-03-191-11/+11
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-164-0/+175
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann2015-03-164-2/+415
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann2015-03-164-2/+600
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann2015-03-164-24/+493
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+2Star
* cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-9/+1Star
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