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* target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann2015-05-301-1/+1
* target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann2015-05-301-11/+0Star
* target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann2015-05-301-1/+1
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-224-0/+74
* target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+21
* target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+29
* target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2015-05-222-0/+11
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-224-0/+19
* target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+44
* target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+40
* target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann2015-05-221-2/+9
* target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann2015-05-222-3/+8
* target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann2015-05-221-0/+8
* target-tricore: fix rfe not restoring the PCBastian Koppelmann2015-05-111-0/+1
* target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann2015-05-111-1/+1
* target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann2015-05-111-2/+2
* target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann2015-05-111-1/+1
* tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite2015-04-301-5/+0Star
* target-tricore: Fix check which was always falseStefan Weil2015-04-041-1/+1
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
* target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann2015-03-241-30/+10Star
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
* target-tricore: Fix two helper functions (clang warnings)Stefan Weil2015-03-241-6/+6
* Fix typos in commentsViswesh2015-03-191-11/+11
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-164-0/+175
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann2015-03-164-2/+415
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann2015-03-164-2/+600
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann2015-03-164-24/+493
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+2Star
* cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-9/+1Star
* target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann2015-03-033-0/+418
* target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann2015-03-034-4/+588
* target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann2015-03-033-0/+534
* target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann2015-03-032-15/+136
* target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann2015-03-031-6/+21
* target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann2015-03-031-2/+2
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-3/+1Star
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+0Star
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-274-1/+319
* target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann2015-01-271-0/+70
* target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann2015-01-271-0/+37
* target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann2015-01-271-0/+182
* target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann2015-01-261-15/+26
* target-tricore: Fix bugs found by coverityBastian Koppelmann2015-01-262-1/+3
* target-tricore: calculate av bits before saturationBastian Koppelmann2015-01-261-12/+16
* target-tricore: Several translator and cpu model fixesBastian Koppelmann2015-01-263-4/+5
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