index
:
bwlp/qemu.git
block_qcow2_cluster_info
master
spice_video_codecs
Experimental fork of QEMU with video encoding patches
OpenSLX
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
target
/
arm
/
helper-a64.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
arm tcg cpus: Fix Lesser GPL version number
Chetan Pant
2020-11-15
1
-1
/
+1
*
target/arm: Add helper_mte_check_zva
Richard Henderson
2020-06-26
1
-0
/
+1
*
target/arm: Add gen_mte_checkN
Richard Henderson
2020-06-26
1
-0
/
+1
*
target/arm: Add gen_mte_check1
Richard Henderson
2020-06-26
1
-0
/
+1
*
target/arm: Implement the LDGM, STGM, STZGM instructions
Richard Henderson
2020-06-26
1
-0
/
+3
*
target/arm: Implement LDG, STG, ST2G instructions
Richard Henderson
2020-06-26
1
-0
/
+7
*
target/arm: Implement the ADDG, SUBG instructions
Richard Henderson
2020-06-26
1
-0
/
+1
*
target/arm: Implement the IRG instruction
Richard Henderson
2020-06-26
1
-0
/
+2
*
target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
Richard Henderson
2020-03-05
1
-1
/
+1
*
target/arm: Move helper_dc_zva to helper-a64.c
Richard Henderson
2020-03-05
1
-0
/
+1
*
target/arm: Split helper_msr_i_pstate into 3
Richard Henderson
2019-03-05
1
-0
/
+3
*
target/arm: Add new_pc argument to helper_exception_return
Richard Henderson
2019-01-21
1
-1
/
+1
*
target/arm: Move helper_exception_return to helper-a64.c
Richard Henderson
2019-01-21
1
-0
/
+2
*
target/arm: Add PAuth helpers
Richard Henderson
2019-01-21
1
-0
/
+12
*
target/arm: Implement FCMP for fp16
Alex Bennée
2018-05-15
1
-0
/
+2
*
target/arm: Implement CAS and CASP
Richard Henderson
2018-05-10
1
-0
/
+2
*
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
Alex Bennée
2018-03-01
1
-0
/
+1
*
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
Alex Bennée
2018-03-01
1
-0
/
+1
*
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
Alex Bennée
2018-03-01
1
-0
/
+2
*
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
Alex Bennée
2018-03-01
1
-0
/
+2
*
arm/translate-a64: add FP16 x2 ops for simd_indexed
Alex Bennée
2018-03-01
1
-0
/
+10
*
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
Alex Bennée
2018-03-01
1
-0
/
+2
*
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
Alex Bennée
2018-03-01
1
-0
/
+2
*
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
Alex Bennée
2018-03-01
1
-0
/
+5
*
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
Alex Bennée
2018-03-01
1
-0
/
+4
*
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
Alex Bennée
2018-03-01
1
-0
/
+4
*
target/arm: check CF_PARALLEL instead of parallel_cpus
Emilio G. Cota
2017-10-24
1
-0
/
+4
*
target-arm: Use clrsb helper
Richard Henderson
2017-01-10
1
-2
/
+0
*
target-arm: Use clz opcode
Richard Henderson
2017-01-10
1
-2
/
+0
*
Move target-* CPU file into a target/ folder
Thomas Huth
2016-12-20
1
-0
/
+50
