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path: root/target/arm/helper-a64.h
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* target/arm: Split helper_msr_i_pstate into 3Richard Henderson2019-03-051-0/+3
* target/arm: Add new_pc argument to helper_exception_returnRichard Henderson2019-01-211-1/+1
* target/arm: Move helper_exception_return to helper-a64.cRichard Henderson2019-01-211-0/+2
* target/arm: Add PAuth helpersRichard Henderson2019-01-211-0/+12
* target/arm: Implement FCMP for fp16Alex Bennée2018-05-151-0/+2
* target/arm: Implement CAS and CASPRichard Henderson2018-05-101-0/+2
* arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+1
* arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+1
* arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+2
* arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+2
* arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée2018-03-011-0/+10
* arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée2018-03-011-0/+2
* arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée2018-03-011-0/+2
* arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée2018-03-011-0/+5
* arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée2018-03-011-0/+4
* arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée2018-03-011-0/+4
* target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-0/+4
* target-arm: Use clrsb helperRichard Henderson2017-01-101-2/+0Star
* target-arm: Use clz opcodeRichard Henderson2017-01-101-2/+0Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+50
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