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path: root/target/arm/helper.c
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* target/arm: Extend PAR format determinationEdgar E. Iglesias2017-12-131-4/+29
* target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()Peter Maydell2017-12-131-31/+14Star
* target/arm: Ignore fsr from get_phys_addr() in do_ats_write()Peter Maydell2017-12-131-6/+10
* target/arm: Convert get_phys_addr_pmsav8() to not return FSC valuesPeter Maydell2017-12-131-11/+18
* target/arm: Convert get_phys_addr_pmsav7() to not return FSC valuesPeter Maydell2017-12-131-4/+7
* target/arm: Convert get_phys_addr_pmsav5() to not return FSC valuesPeter Maydell2017-12-131-7/+13
* target/arm: Convert get_phys_addr_lpae() to not return FSC valuesPeter Maydell2017-12-131-23/+18Star
* target/arm: Convert get_phys_addr_v6() to not return FSC valuesPeter Maydell2017-12-131-18/+22
* target/arm: Convert get_phys_addr_v5() to not return FSC valuesPeter Maydell2017-12-131-15/+18
* target/arm: Remove fsr argument from arm_ld*_ptw()Peter Maydell2017-12-131-13/+11Star
* target/arm: Implement TT instructionPeter Maydell2017-12-131-0/+108
* target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8()Peter Maydell2017-12-131-51/+79
* target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell2017-12-131-4/+7
* target/arm: Add missing M profile case to regime_is_user()Peter Maydell2017-12-131-0/+1
* target/arm: Allow explicit writes to CONTROL.SPSEL in Handler modePeter Maydell2017-12-131-1/+4
* target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP readsPeter Maydell2017-12-131-6/+4Star
* arm: check regime, not current state, for ATS write PAR formatPeter Maydell2017-11-201-1/+1
* target/arm: Report GICv3 sysregs present in ID registers if neededPeter Maydell2017-11-201-4/+40
* arm: implement cache/shareability attribute bits for PAR registersAndrew Baumann2017-11-071-14/+164
* target/arm: Implement secure function returnPeter Maydell2017-10-121-8/+107
* target/arm: Implement BLXNSPeter Maydell2017-10-121-0/+59
* target/arm: Implement SG instructionPeter Maydell2017-10-121-5/+127
* target/arm: Implement security attribute lookups for memory accessesPeter Maydell2017-10-061-2/+180
* target/arm: Add v8M support to exception entry codePeter Maydell2017-10-061-20/+145
* target/arm: Add support for restoring v8M additional state contextPeter Maydell2017-10-061-0/+30
* target/arm: Update excret sanity checks for v8MPeter Maydell2017-10-061-15/+58
* target/arm: Don't warn about exception return with PC low bit set for v8MPeter Maydell2017-10-061-7/+15
* target/arm: Warn about restoring to unaligned stackPeter Maydell2017-10-061-0/+7
* target/arm: Check for xPSR mismatch usage faults earlier for v8MPeter Maydell2017-10-061-3/+27
* target/arm: Restore SPSEL to correct CONTROL register on exception returnPeter Maydell2017-10-061-13/+27
* target/arm: Restore security state on exception returnPeter Maydell2017-10-061-0/+2
* target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler modePeter Maydell2017-10-061-22/+43
* target/arm: Don't switch to target stack early in v7M exception returnPeter Maydell2017-10-061-32/+98
* arm: Fix SMC reporting to EL2 when QEMU provides PSCIJan Kiszka2017-10-061-1/+8
* nvic: Support banked exceptions in acknowledge and completePeter Maydell2017-09-211-3/+5
* nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell2017-09-211-10/+14
* target/arm: Implement MSR/MRS access to NS banked registersPeter Maydell2017-09-211-0/+110
* target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()Peter Maydell2017-09-141-11/+12
* target/arm: Add and use defines for EXCRET constantsPeter Maydell2017-09-141-5/+9
* target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()Peter Maydell2017-09-141-2/+2
* target/arm: Get PRECISERR and IBUSERR the right way roundPeter Maydell2017-09-141-4/+4
* target/arm: Clear exclusive monitor on v7M reset, exception entry/exitPeter Maydell2017-09-141-0/+2
* target/arm: Implement BXNS, and banked stack pointersPeter Maydell2017-09-071-0/+79
* target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell2017-09-071-26/+0Star
* target/arm: Make CFSR register banked for v8MPeter Maydell2017-09-071-9/+9
* target/arm: Make MMFAR banked for v8MPeter Maydell2017-09-071-2/+2
* target/arm: Make CCR register banked for v8MPeter Maydell2017-09-071-2/+3
* target/arm: Make MPU_CTRL register banked for v8MPeter Maydell2017-09-071-2/+3
* target/arm: Make MPU_RNR register banked for v8MPeter Maydell2017-09-071-3/+3
* target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell2017-09-071-5/+6
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