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path: root/target/arm/helper.c
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* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-2/+2
* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne2021-03-051-1/+1
* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran2021-03-051-0/+37
* target/arm: Correctly initialize MDCR_EL2.HPMNDaniel Müller2021-02-111-5/+4Star
* target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstateRebecca Cran2021-02-111-6/+18
* target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran2021-02-111-0/+22
* target/arm: Fix SCR RES1 handlingMike Nawrocki2021-02-111-2/+14
* target/arm: do not use cc->do_interrupt for KVM directlyClaudio Fontana2021-02-051-0/+4
* target/arm: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2021-01-291-1/+1
* target/arm: Conditionalize DBGDIDRRichard Henderson2021-01-291-6/+15
* target/arm: Implement ID_PFR2Richard Henderson2021-01-291-2/+2
* target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont2021-01-191-14/+11Star
* target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont2021-01-191-3/+16
* target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont2021-01-191-0/+6
* target/arm: secure stage 2 translation regimeRémi Denis-Courmont2021-01-191-24/+54
* target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont2021-01-191-7/+6Star
* target/arm: translate NS bit in page-walksRémi Denis-Courmont2021-01-191-0/+12
* target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont2021-01-191-3/+6
* target/arm: handle VMID change in secure stateRémi Denis-Courmont2021-01-191-4/+9
* target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont2021-01-191-0/+24
* target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont2021-01-191-43/+84
* target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont2021-01-191-5/+5
* target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont2021-01-191-16/+22
* target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont2021-01-191-13/+18
* target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont2021-01-191-20/+13Star
* target/arm: remove redundant testsRémi Denis-Courmont2021-01-191-6/+4Star
* semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-181-2/+3
* target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-181-1/+1
* target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont2021-01-121-2/+13
* target/arm: Fix MTE0_ACTIVERichard Henderson2021-01-081-1/+1
* qapi: Use QAPI_LIST_PREPEND() where possibleEric Blake2020-12-191-5/+1Star
* target/arm: Implement v8.1M PXN extensionPeter Maydell2020-12-101-1/+6
* target/arm: fix stage 2 page-walks in 32-bit emulationRémi Denis-Courmont2020-11-231-2/+2
* target/arm: add spaces around operatorXinhao Zhang2020-11-101-1/+1
* target/arm: fix LORID_EL1 access checkRémi Denis-Courmont2020-11-021-14/+5Star
* target/arm: fix handling of HCR.FBRémi Denis-Courmont2020-11-021-3/+2Star
* target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11Richard Henderson2020-10-201-4/+5
* target/arm: Use tlb_flush_page_bits_by_mmuidx*Richard Henderson2020-10-201-7/+39
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-051-2/+2
* cpu-timers, icount: new modulesClaudio Fontana2020-10-051-1/+2
* target/arm: Move id_pfr0, id_pfr1 into ARMISARegistersPeter Maydell2020-10-011-2/+2
* target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA checkPeter Maydell2020-10-011-2/+3
* target/arm: Count PMU events when MDCR.SPME is setAaron Lindsay2020-09-141-1/+1
* target/arm: Clarify HCR_EL2 ARMCPRegInfo typePhilippe Mathieu-Daudé2020-08-281-1/+0Star
* target/arm: Convert A32 coprocessor insns to decodetreePeter Maydell2020-08-241-0/+29
* target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64Peter Maydell2020-08-051-1/+91
* target/arm: Always pass cacheattr in S1_ptw_translateRichard Henderson2020-07-271-13/+6Star
* target/arm: Don't do raw writes for PMINTENCLRAaron Lindsay2020-07-131-2/+2
* target/arm: Cache the Tagged bit for a page in MemTxAttrsRichard Henderson2020-06-261-3/+45
* target/arm: Always pass cacheattr to get_phys_addrRichard Henderson2020-06-261-30/+30
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