| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 2020-11-15 | 1 | -1/+1 |
| * | target/arm: Convert T16, long branches | Richard Henderson | 2019-09-05 | 1 | -0/+7 |
| * | target/arm: Convert T16, Unconditional branch | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Convert T16, load (literal) | Richard Henderson | 2019-09-05 | 1 | -0/+4 |
| * | target/arm: Convert T16, shift immediate | Richard Henderson | 2019-09-05 | 1 | -0/+8 |
| * | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson | 2019-09-05 | 1 | -10/+21 |
| * | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson | 2019-09-05 | 1 | -0/+12 |
| * | target/arm: Convert T16, push and pop | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert T16, nop hints | Richard Henderson | 2019-09-05 | 1 | -0/+17 |
| * | target/arm: Convert T16, Reverse bytes | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert T16, Change processor state | Richard Henderson | 2019-09-05 | 1 | -0/+12 |
| * | target/arm: Convert T16, extract | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert T16 branch and exchange | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2019-09-05 | 1 | -0/+11 |
| * | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2019-09-05 | 1 | -0/+16 |
| * | target/arm: Convert T16 load/store multiple | Richard Henderson | 2019-09-05 | 1 | -0/+8 |
| * | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2019-09-05 | 1 | -0/+7 |
| * | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2019-09-05 | 1 | -0/+33 |
| * | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2019-09-05 | 1 | -0/+15 |
| * | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2019-09-05 | 1 | -0/+36 |
| * | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 2019-09-05 | 1 | -0/+20 |
