| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Implement MVE VCTP | Peter Maydell | 2021-08-25 | 1 | -0/+1 |
| * | target/arm: Implement MVE shifts by register | Peter Maydell | 2021-07-02 | 1 | -4/+14 |
| * | target/arm: Implement MVE shifts by immediate | Peter Maydell | 2021-07-02 | 1 | -8/+25 |
| * | target/arm: Implement MVE long shifts by register | Peter Maydell | 2021-07-02 | 1 | -3/+13 |
| * | target/arm: Implement MVE long shifts by immediate | Peter Maydell | 2021-07-02 | 1 | -0/+28 |
| * | target/arm: Implement MVE LETP insn | Peter Maydell | 2021-06-16 | 1 | -1/+1 |
| * | target/arm: Implement MVE DLSTP | Peter Maydell | 2021-06-16 | 1 | -3/+6 |
| * | target/arm: Implement MVE WLSTP insn | Peter Maydell | 2021-06-16 | 1 | -2/+6 |
| * | target/arm: Implement MVE LCTP | Peter Maydell | 2021-06-16 | 1 | -0/+2 |
| * | target/arm: Implement M-profile "minimal RAS implementation" | Peter Maydell | 2020-12-10 | 1 | -0/+4 |
| * | target/arm: Implement CLRM instruction | Peter Maydell | 2020-12-10 | 1 | -1/+5 |
| * | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 2020-11-15 | 1 | -1/+1 |
| * | target/arm: Implement v8.1M low-overhead-loop instructions | Peter Maydell | 2020-10-20 | 1 | -0/+8 |
| * | target/arm: Implement v8.1M branch-future insns (as NOPs) | Peter Maydell | 2020-10-20 | 1 | -1/+12 |
| * | target/arm: Make the t32 insn[25:23]=111 group non-overlapping | Peter Maydell | 2020-10-20 | 1 | -13/+11 |
| * | target/arm: Implement v8.1M conditional-select insns | Peter Maydell | 2020-10-20 | 1 | -0/+3 |
| * | target/arm: Convert T32 coprocessor insns to decodetree | Peter Maydell | 2020-08-24 | 1 | -0/+19 |
| * | target/arm: Use a non-overlapping group for misc control | Richard Henderson | 2020-06-09 | 1 | -2/+2 |
| * | target/arm: Convert TT | Richard Henderson | 2019-09-05 | 1 | -1/+4 |
| * | target/arm: Convert SG | Richard Henderson | 2019-09-05 | 1 | -1/+4 |
| * | target/arm: Convert Table Branch | Richard Henderson | 2019-09-05 | 1 | -1/+7 |
| * | target/arm: Convert CPS (privileged) | Richard Henderson | 2019-09-05 | 1 | -0/+5 |
| * | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert RFE and SRS | Richard Henderson | 2019-09-05 | 1 | -0/+12 |
| * | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 2019-09-05 | 1 | -34/+51 |
| * | target/arm: Convert LDM, STM | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert MOVW, MOVT | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson | 2019-09-05 | 1 | -0/+18 |
| * | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson | 2019-09-05 | 1 | -1/+36 |
| * | target/arm: Convert Parallel addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -0/+44 |
| * | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson | 2019-09-05 | 1 | -0/+19 |
| * | target/arm: Convert Synchronization primitives | Richard Henderson | 2019-09-05 | 1 | -0/+46 |
| * | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson | 2019-09-05 | 1 | -0/+141 |
| * | target/arm: Convert T32 ADDW/SUBW | Richard Henderson | 2019-09-05 | 1 | -0/+19 |
| * | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson | 2019-09-05 | 1 | -0/+5 |
| * | target/arm: Convert ERET | Richard Henderson | 2019-09-05 | 1 | -0/+8 |
| * | target/arm: Convert CLZ | Richard Henderson | 2019-09-05 | 1 | -0/+5 |
| * | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson | 2019-09-05 | 1 | -0/+2 |
| * | target/arm: Convert Cyclic Redundancy Check | Richard Henderson | 2019-09-05 | 1 | -0/+7 |
| * | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson | 2019-09-05 | 1 | -12/+34 |
| * | target/arm: Convert MSR (immediate) and hints | Richard Henderson | 2019-09-05 | 1 | -0/+17 |
| * | target/arm: Convert Halfword multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -0/+29 |
| * | target/arm: Convert Saturating addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -0/+19 |
| * | target/arm: Convert Data Processing (immediate) | Richard Henderson | 2019-09-05 | 1 | -0/+42 |
| * | target/arm: Convert Data Processing (reg-shifted-reg) | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Convert Data Processing (register) | Richard Henderson | 2019-09-05 | 1 | -0/+43 |
| * | target/arm: Add stubs for aa32 decodetree | Richard Henderson | 2019-09-05 | 1 | -0/+20 |
