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path: root/target/arm/tlb_helper.c
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* target/arm: Use softmmu tlbs for page table walkingRichard Henderson2022-10-201-3/+14
* target/arm: Use probe_access_full for MTERichard Henderson2022-10-201-4/+0Star
* target/arm: Enable TARGET_PAGE_ENTRY_EXTRARichard Henderson2022-10-201-0/+3
* target/arm: Use tlb_set_page_fullRichard Henderson2022-10-101-5/+4Star
* target/arm: Create GetPhysAddrResultRichard Henderson2022-09-221-13/+9Star
* target/arm: Fold regime_tcr() and regime_tcr_value() togetherPeter Maydell2022-07-181-1/+1
* target/arm: Define and use new regime_tcr_value() functionPeter Maydell2022-07-181-1/+1
* target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.cRichard Henderson2022-06-081-0/+26
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-3/+4
* target/arm: Take an exception if PC is misalignedRichard Henderson2021-12-151-0/+18
* target/arm: Split compute_fsr_fsc out of arm_deliver_faultRichard Henderson2021-12-151-17/+28
* target/arm: Implement arm_cpu_record_sigbusRichard Henderson2021-11-021-0/+6
* target/arm: Implement arm_cpu_record_sigsegvRichard Henderson2021-11-021-17/+19
* target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fillRichard Henderson2021-03-231-0/+1
* linux-user/aarch64: Pass syndrome to EXC_*_ABORTRichard Henderson2021-02-161-6/+9
* target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont2021-01-191-0/+3
* target/arm: Cache the Tagged bit for a page in MemTxAttrsRichard Henderson2020-06-261-0/+5
* target/arm: Always pass cacheattr to get_phys_addrRichard Henderson2020-06-261-1/+3
* target/arm: Define arm_cpu_do_unaligned_access for user-onlyRichard Henderson2020-06-261-2/+2
* target-arm: kvm64: handle SIGBUS signal from kernel or KVMDongjiu Geng2020-05-141-1/+1
* target/arm: Return correct IL bit in merge_syn_data_abortJeff Kubascik2020-01-171-1/+1
* target/arm: Move TLB related routines to tlb_helper.cPhilippe Mathieu-Daudé2019-07-011-0/+200