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path: root/target/arm/translate-vfp.inc.c
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* target/arm: Split VMINMAXNM decodeRichard Henderson2020-02-281-73/+36Star
* target/arm: Split VFM decodeRichard Henderson2020-02-281-6/+46
* target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson2020-02-281-0/+39
* target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson2020-02-281-4/+18
* target/arm: Add missing checks for fpsp_v2Richard Henderson2020-02-281-9/+69
* target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson2020-02-281-16/+8Star
* target/arm: Perform fpdp_v2 check firstRichard Henderson2020-02-281-69/+71
* target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson2020-02-281-20/+20
* target/arm: Rename isar_feature_aa32_simd_r32Richard Henderson2020-02-211-26/+27
* target/arm: Handle trapping to EL2 of AArch32 VMRS instructionsMarc Zyngier2019-12-161-3/+15
* target/arm: Allow reading flags from FPSCR for M-profileChristophe Lyon2019-11-011-2/+3
* target/arm: Free TCG temps in trans_VMOV_64_sp()Peter Maydell2019-09-031-0/+2
* target/arm: Factor out unallocated_encoding for aarch32Richard Henderson2019-09-031-2/+1Star
* Revert "target/arm: Use unallocated_encoding for aarch32"Richard Henderson2019-09-031-1/+2
* target/arm: Use unallocated_encoding for aarch32Richard Henderson2019-08-161-2/+1Star
* target/arm: Replace offset with pc in gen_exception_insnRichard Henderson2019-08-161-3/+3
* target/arm: Introduce add_reg_for_litRichard Henderson2019-08-161-30/+8Star
* target/arm: Correct VMOV_imm_dp handling of short vectorsPeter Maydell2019-07-041-1/+1
* target/arm: Check for dp support for dp VFM, not spPeter Maydell2019-06-181-4/+4
* target/arm: Only implement doubles if the FPU supports themPeter Maydell2019-06-171-0/+84
* target/arm: Fix typos in trans function prototypesPeter Maydell2019-06-171-14/+14
* target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_immPeter Maydell2019-06-171-24/+4Star
* target/arm: Move vfp_expand_imm() to translate.[ch]Peter Maydell2019-06-171-0/+33
* target/arm: Fix short-vector increment behaviourPeter Maydell2019-06-131-40/+60
* target/arm: Convert float-to-integer VCVT insns to decodetreePeter Maydell2019-06-131-0/+72
* target/arm: Convert VCVT fp/fixed-point conversion insns to decodetreePeter Maydell2019-06-131-0/+124
* target/arm: Convert VJCVT to decodetreePeter Maydell2019-06-131-0/+28
* target/arm: Convert integer-to-float insns to decodetreePeter Maydell2019-06-131-0/+58
* target/arm: Convert double-single precision conversion insns to decodetreePeter Maydell2019-06-131-0/+48
* target/arm: Convert VFP round insns to decodetreePeter Maydell2019-06-131-0/+163
* target/arm: Convert the VCVT-to-f16 insns to decodetreePeter Maydell2019-06-131-0/+62
* target/arm: Convert the VCVT-from-f16 insns to decodetreePeter Maydell2019-06-131-0/+82
* target/arm: Convert VFP comparison insns to decodetreePeter Maydell2019-06-131-0/+75
* target/arm: Convert VMOV (register) to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VSQRT to decodetreePeter Maydell2019-06-131-0/+20
* target/arm: Convert VNEG to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VABS to decodetreePeter Maydell2019-06-131-0/+167
* target/arm: Convert VMOV (imm) to decodetreePeter Maydell2019-06-131-0/+129
* target/arm: Convert VFP fused multiply-add insns to decodetreePeter Maydell2019-06-131-0/+121
* target/arm: Convert VDIV to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VSUB to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VADD to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VNMUL to decodetreePeter Maydell2019-06-131-0/+24
* target/arm: Convert VMUL to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VFP VNMLA to decodetreePeter Maydell2019-06-131-0/+34
* target/arm: Convert VFP VNMLS to decodetreePeter Maydell2019-06-131-0/+42
* target/arm: Convert VFP VMLS to decodetreePeter Maydell2019-06-131-0/+38
* target/arm: Convert VFP VMLA to decodetreePeter Maydell2019-06-131-0/+205
* target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0dPeter Maydell2019-06-131-18/+28
* target/arm: Convert the VFP load/store multiple insns to decodetreePeter Maydell2019-06-131-0/+162
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