| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: only update pc after semihosting completes | Alex Bennée | 2020-01-09 | 1 | -3/+3 |
| * | target/arm: ensure we use current exception state after SCR update | Alex Bennée | 2019-12-16 | 1 | -1/+5 |
| * | target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 | Marc Zyngier | 2019-12-16 | 1 | -1/+2 |
| * | target/arm: Relax r13 restriction for ldrex/strex for v8.0 | Richard Henderson | 2019-11-19 | 1 | -4/+8 |
| * | target/arm: Do not reject rt == rt2 for strexd | Richard Henderson | 2019-11-19 | 1 | -1/+1 |
| * | target/arm: Rebuild hflags for M-profile | Richard Henderson | 2019-10-24 | 1 | -1/+4 |
| * | target/arm: Rebuild hflags at MSR writes | Richard Henderson | 2019-10-24 | 1 | -5/+23 |
| * | target/arm: Fix sign-extension for SMLAL* | Richard Henderson | 2019-10-22 | 1 | -1/+3 |
| * | target/arm: handle A-profile semihosting at translate time | Alex Bennée | 2019-09-27 | 1 | -4/+15 |
| * | target/arm: handle M-profile semihosting at translate time | Alex Bennée | 2019-09-27 | 1 | -1/+10 |
| * | target/arm: Inline gen_bx_im into callers | Richard Henderson | 2019-09-05 | 1 | -19/+7 |
| * | target/arm: Clean up disas_thumb_insn | Richard Henderson | 2019-09-05 | 1 | -25/+2 |
| * | target/arm: Convert T16, long branches | Richard Henderson | 2019-09-05 | 1 | -49/+36 |
| * | target/arm: Convert T16, Unconditional branch | Richard Henderson | 2019-09-05 | 1 | -7/+2 |
| * | target/arm: Convert T16, load (literal) | Richard Henderson | 2019-09-05 | 1 | -40/+2 |
| * | target/arm: Convert T16, shift immediate | Richard Henderson | 2019-09-05 | 1 | -24/+2 |
| * | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson | 2019-09-05 | 1 | -77/+34 |
| * | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson | 2019-09-05 | 1 | -23/+3 |
| * | target/arm: Convert T16, push and pop | Richard Henderson | 2019-09-05 | 1 | -71/+12 |
| * | target/arm: Split gen_nop_hint | Richard Henderson | 2019-09-05 | 1 | -43/+24 |
| * | target/arm: Convert T16, nop hints | Richard Henderson | 2019-09-05 | 1 | -2/+1 |
| * | target/arm: Convert T16, Reverse bytes | Richard Henderson | 2019-09-05 | 1 | -15/+3 |
| * | target/arm: Convert T16, Change processor state | Richard Henderson | 2019-09-05 | 1 | -46/+38 |
| * | target/arm: Convert T16, extract | Richard Henderson | 2019-09-05 | 1 | -13/+1 |
| * | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 2019-09-05 | 1 | -13/+2 |
| * | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 2019-09-05 | 1 | -47/+2 |
| * | target/arm: Convert T16 branch and exchange | Richard Henderson | 2019-09-05 | 1 | -41/+29 |
| * | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2019-09-05 | 1 | -42/+2 |
| * | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2019-09-05 | 1 | -24/+2 |
| * | target/arm: Convert T16 load/store multiple | Richard Henderson | 2019-09-05 | 1 | -39/+9 |
| * | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2019-09-05 | 1 | -11/+1 |
| * | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2019-09-05 | 1 | -89/+5 |
| * | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2019-09-05 | 1 | -49/+2 |
| * | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2019-09-05 | 1 | -145/+7 |
| * | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Simplify disas_arm_insn | Richard Henderson | 2019-09-05 | 1 | -53/+16 |
| * | target/arm: Simplify disas_thumb2_insn | Richard Henderson | 2019-09-05 | 1 | -76/+3 |
| * | target/arm: Convert TT | Richard Henderson | 2019-09-05 | 1 | -60/+30 |
| * | target/arm: Convert SG | Richard Henderson | 2019-09-05 | 1 | -22/+29 |
| * | target/arm: Convert Table Branch | Richard Henderson | 2019-09-05 | 1 | -23/+34 |
| * | target/arm: Convert Unallocated memory hint | Richard Henderson | 2019-09-05 | 1 | -8/+0 |
| * | target/arm: Convert PLI, PLD, PLDW | Richard Henderson | 2019-09-05 | 1 | -17/+20 |
| * | target/arm: Convert SETEND | Richard Henderson | 2019-09-05 | 1 | -9/+13 |
| * | target/arm: Convert CPS (privileged) | Richard Henderson | 2019-09-05 | 1 | -51/+40 |
| * | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson | 2019-09-05 | 1 | -69/+58 |
| * | target/arm: Convert RFE and SRS | Richard Henderson | 2019-09-05 | 1 | -89/+55 |
| * | target/arm: Convert SVC | Richard Henderson | 2019-09-05 | 1 | -6/+13 |
| * | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 2019-09-05 | 1 | -75/+58 |
| * | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -2/+3 |
| * | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -8/+18 |
