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path: root/target/arm/translate.c
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* target/arm: Implement TT instructionPeter Maydell2017-12-131-1/+28
* target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell2017-12-131-2/+6
* target/arm: Generate UNDEF for 32-bit Thumb2 insnsPeter Maydell2017-12-111-1/+4
* translate.c: Fix usermode big-endian AArch32 LDREXD and STREXDPeter Maydell2017-11-071-5/+34
* fix WFI/WFE length in syndrome registerStefano Stabellini2017-10-311-1/+9
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-2/+1Star
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-2/+1Star
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-4/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-2/+7
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
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* target/arm: Implement SG instruction corner casesPeter Maydell2017-10-121-1/+22
* target/arm: Support some Thumb insns being always unconditionalPeter Maydell2017-10-121-1/+47
* target-arm: Simplify insn_crosses_page()Peter Maydell2017-10-121-21/+6Star
* target/arm: Pull Thumb insn word loads up to top levelPeter Maydell2017-10-121-70/+108
* target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1Peter Maydell2017-10-121-2/+1Star
* target/arm: Implement secure function returnPeter Maydell2017-10-121-2/+12
* target/arm: Implement BLXNSPeter Maydell2017-10-121-2/+15
* target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()Peter Maydell2017-10-121-0/+4
* tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota2017-10-101-4/+1Star
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell2017-09-071-4/+50
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| * target/arm: Add Jazelle featurePortia Stephens2017-09-071-1/+1
| * target/arm: Implement BXNS, and banked stack pointersPeter Maydell2017-09-071-1/+41
| * target/arm: Make CONTROL register banked for v8MPeter Maydell2017-09-071-1/+1
| * target/arm: Add state field, feature bit and migration for v8M secure statePeter Maydell2017-09-071-1/+7
* | target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson2017-09-061-25/+33
* | target/arm: Split out thumb_tr_translate_insnRichard Henderson2017-09-061-41/+80
* | target/arm: Move ss check to init_disas_contextRichard Henderson2017-09-061-5/+8
* | target/arm: [tcg] Port to generic translation frameworkLluís Vilanova2017-09-061-87/+22Star
* | target/arm: [tcg] Port to disas_logLluís Vilanova2017-09-061-5/+13
* | target/arm: [tcg] Port to tb_stopLluís Vilanova2017-09-061-77/+84
* | target/arm: [tcg] Port to translate_insnLluís Vilanova2017-09-061-75/+90
* | target/arm: [tcg,a64] Port to insn_startLluís Vilanova2017-09-061-20/+35
* | target/arm: [tcg] Port to insn_startLluís Vilanova2017-09-061-4/+11
* | target/arm: [tcg] Port to tb_startLluís Vilanova2017-09-061-38/+44
* | target/arm: [tcg] Port to init_disas_contextLluís Vilanova2017-09-061-38/+50
* | target/arm: [tcg] Port to DisasContextBaseLluís Vilanova2017-09-061-59/+58Star
* | target/arm: Delay check for magic kernel pageRichard Henderson2017-09-061-11/+11
* | target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-1/+1
* | target/arm: Use DISAS_NORETURNRichard Henderson2017-09-061-6/+8
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* target/arm: Make arm_cpu_dump_state() handle the M-profile XPSRPeter Maydell2017-09-041-18/+40
* target/arm: Tighten up Thumb decode where new v8M insns will bePeter Maydell2017-09-041-9/+39
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+3
* target/arm: optimize aarch32 rev16Aurelien Jarno2017-07-191-2/+4
* target/arm: use DISAS_EXIT for eret handlingAlex Bennée2017-07-171-2/+4
* target/arm: use gen_goto_tb for ISB handlingAlex Bennée2017-07-171-2/+2
* target/arm/translate: ensure gen_goto_tb sets exit flagsAlex Bennée2017-07-171-1/+5
* target/arm/translate: make DISAS_UPDATE match declared semanticsAlex Bennée2017-07-171-3/+3
* target/arm: optimize indirect branchesEmilio G. Cota2017-06-051-9/+16
* target/arm: optimize cross-page direct jumps in softmmuEmilio G. Cota2017-06-051-1/+5
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