| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation | Peter Maydell | 2021-07-02 | 1 | -8/+9 |
| * | target/arm: Check NaN mode before silencing NaN | Joe Komlodi | 2021-07-02 | 2 | -9/+27 |
| * | target/arm: Improve REVSH | Richard Henderson | 2021-06-29 | 1 | -3/+1 |
| * | target/arm: Improve vector REV | Richard Henderson | 2021-06-29 | 1 | -4/+2 |
| * | target/arm: Improve REV32 | Richard Henderson | 2021-06-29 | 1 | -13/+4 |
| * | tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 | Richard Henderson | 2021-06-29 | 2 | -6/+8 |
| * | target/arm: Implement MTE3 | Peter Collingbourne | 2021-06-24 | 2 | -32/+52 |
| * | target/arm: Make VMOV scalar <-> gpreg beatwise for MVE | Peter Maydell | 2021-06-24 | 3 | -8/+75 |
| * | target/arm: Implement MVE VADDV | Peter Maydell | 2021-06-24 | 4 | -0/+76 |
| * | target/arm: Implement MVE VHCADD | Peter Maydell | 2021-06-24 | 4 | -3/+19 |
| * | target/arm: Implement MVE VCADD | Peter Maydell | 2021-06-24 | 4 | -2/+51 |
| * | target/arm: Implement MVE VADC, VSBC | Peter Maydell | 2021-06-24 | 4 | -0/+99 |
| * | target/arm: Implement MVE VRHADD | Peter Maydell | 2021-06-24 | 4 | -0/+19 |
| * | target/arm: Implement MVE VQDMULL (vector) | Peter Maydell | 2021-06-24 | 4 | -0/+70 |
| * | target/arm: Implement MVE VQDMLSDH and VQRDMLSDH | Peter Maydell | 2021-06-24 | 4 | -0/+69 |
| * | target/arm: Implement MVE VQDMLADH and VQRDMLADH | Peter Maydell | 2021-06-24 | 4 | -0/+114 |
| * | target/arm: Implement MVE VRSHL | Peter Maydell | 2021-06-24 | 4 | -0/+17 |
| * | target/arm: Implement MVE VSHL insn | Peter Maydell | 2021-06-24 | 4 | -0/+19 |
| * | target/arm: Implement MVE VQRSHL | Peter Maydell | 2021-06-24 | 4 | -0/+19 |
| * | target/arm: Implement MVE VQSHL (vector) | Peter Maydell | 2021-06-24 | 4 | -0/+56 |
| * | target/arm: Implement MVE VQADD, VQSUB (vector) | Peter Maydell | 2021-06-24 | 4 | -0/+39 |
| * | target/arm: Implement MVE VQDMULH, VQRDMULH (vector) | Peter Maydell | 2021-06-24 | 4 | -0/+40 |
| * | target/arm: Implement MVE VQDMULL scalar | Peter Maydell | 2021-06-24 | 4 | -4/+119 |
| * | target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) | Peter Maydell | 2021-06-24 | 4 | -0/+38 |
| * | target/arm: Implement MVE VQADD and VQSUB | Peter Maydell | 2021-06-24 | 4 | -0/+87 |
| * | target/arm: Implement MVE VPST | Peter Maydell | 2021-06-24 | 2 | -0/+63 |
| * | target/arm: Implement MVE VBRSR | Peter Maydell | 2021-06-24 | 4 | -0/+49 |
| * | target/arm: Implement MVE VHADD, VHSUB (scalar) | Peter Maydell | 2021-06-24 | 4 | -0/+32 |
| * | target/arm: Implement MVE VSUB, VMUL (scalar) | Peter Maydell | 2021-06-24 | 4 | -0/+14 |
| * | target/arm: Implement MVE VADD (scalar) | Peter Maydell | 2021-06-24 | 4 | -0/+78 |
| * | target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH | Peter Maydell | 2021-06-21 | 4 | -0/+76 |
| * | target/arm: Implement MVE VMLSLDAV | Peter Maydell | 2021-06-21 | 4 | -0/+23 |
| * | target/arm: Implement MVE VMLALDAV | Peter Maydell | 2021-06-21 | 5 | -0/+163 |
| * | target/arm: Implement MVE VMULL | Peter Maydell | 2021-06-21 | 4 | -0/+57 |
| * | target/arm: Implement MVE VHADD, VHSUB | Peter Maydell | 2021-06-21 | 4 | -0/+48 |
| * | target/arm: Implement MVE VABD | Peter Maydell | 2021-06-21 | 4 | -0/+17 |
| * | target/arm: Implement MVE VMAX, VMIN | Peter Maydell | 2021-06-21 | 4 | -0/+37 |
| * | target/arm: Implement MVE VRMULH | Peter Maydell | 2021-06-21 | 4 | -0/+34 |
| * | target/arm: Implement MVE VMULH | Peter Maydell | 2021-06-21 | 4 | -0/+38 |
| * | target/arm: Implement MVE VADD, VSUB, VMUL | Peter Maydell | 2021-06-21 | 4 | -0/+47 |
| * | target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR | Peter Maydell | 2021-06-21 | 4 | -0/+78 |
| * | target/arm: Implement MVE VDUP | Peter Maydell | 2021-06-21 | 4 | -0/+55 |
| * | target/arm: Implement MVE VNEG | Peter Maydell | 2021-06-21 | 4 | -0/+35 |
| * | target/arm: Implement MVE VABS | Peter Maydell | 2021-06-21 | 4 | -0/+37 |
| * | target/arm: Implement MVE VMVN (register) | Peter Maydell | 2021-06-21 | 4 | -0/+14 |
| * | target/arm: Implement MVE VREV16, VREV32, VREV64 | Peter Maydell | 2021-06-21 | 4 | -0/+51 |
| * | target/arm: Implement MVE VCLS | Peter Maydell | 2021-06-21 | 4 | -0/+13 |
| * | target/arm: Implement MVE VCLZ | Peter Maydell | 2021-06-21 | 4 | -0/+132 |
| * | target/arm: Implement widening/narrowing MVE VLDR/VSTR insns | Peter Maydell | 2021-06-21 | 4 | -2/+58 |
| * | target/arm: Implement MVE VLDR/VSTR (non-widening forms) | Peter Maydell | 2021-06-21 | 7 | -0/+351 |
